📄 ask_moden.mdl
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LogVarNameModifier "rt_"
MatFileLogging off
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
EnableShiftOperators on
ParenthesesLevel "Nominal"
SystemTargetFile "grt.tlc"
DialogCategory 0
}
PropName "Components"
}
}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType DiscretePulseGenerator
PulseType "Sample based"
TimeSource "Use simulation time"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
SampleTime "1"
VectorParams1D on
}
Block {
BlockType Scope
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "ask_moden"
Location [93, 211, 982, 849]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "105"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "GND"
Ports [0, 1]
Position [200, 326, 215, 344]
ForegroundColor "blue"
ShowName off
SourceBlock "bus_alteradspbuilder/GND"
SourceType "SGND AlteraBlockSet"
ncstsamp "1"
}
Block {
BlockType Reference
Name "Increment\nDecrement"
Ports [2, 1]
Position [245, 303, 300, 347]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Increment\nDecrement"
SourceType "HDLEntity AlteraBlockSet"
BusType "Unsigned Integer"
bwl "8"
bwr "0"
direction "Increment"
cst_display "0"
cst "0"
clken on
MaskValue "1"
ntsamp "-1"
SIGNALCOMPILER_PARAMS "HDLInputPortsMappingAltera;ena.1.0.b;HDLOutputP"
"ortsMappingAltera;result.8.0.u;HDLParameterMappingAltera;lpm_width.8.natural,"
"cst_val.\"00000000\".string,lpm.0.natural,isunsigned.1.natural,SequenceLength"
".1.natural,SequenceValue.1.natural,direction.0.natural;HDLImplicitPortsMappin"
"gAltera;clock.clock, 2.sclror;HDLComponentNameAltera;IncDec;BusType;Unsigned "
"Integer;bwl;8;bwr;0;clken;on;cst;0;direction;Increment;"
}
Block {
BlockType Reference
Name "Input"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [150, 262, 215, 278]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input"
ppat "E:\\sunyu\\PGC\\dspbuild\\200651000756-99\\ASK"
"\\DSPBuilder_ask_moden"
nSgCpl "1"
SIGNALCOMPILER_PARAMS "sgn;Single Bit;nodetype;Input Port;bwl;1;bwr;0;"
"sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "LUT"
Ports [1, 1]
Position [330, 305, 420, 345]
ForegroundColor "blue"
SourceBlock "gate_alteradspbuilder/LUT"
SourceType "LUT AlteraBlockSet"
BusType "Signed Integer"
bwl "8"
bwr "0"
bwaddr "8"
MatlabArray "127*sin( [0:2*pi/(2^8):2*pi] )"
LocPin "ask_modenLUT"
lpm off
modulename "E:\\sunyu\\PGC\\dspbuild\\200651000756-99\\ASK"
"\\DSPBuilder_ask_moden\\ask_modenLUT.lut"
pipeline off
IslibDir "0"
clken off
ena off
SIGNALCOMPILER_PARAMS "BusType;Signed Integer;bwl;8;bwr;0;bwaddr;8;lpm"
";off;pipeline;off;clken;off;LocPin;ask_modenLUT;ena;off"
}
Block {
BlockType Reference
Name "Output"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [465, 262, 530, 278]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Output"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Output Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
SIGNALCOMPILER_PARAMS "sgn;Signed Integer;nodetype;Output Port;bwl;1;b"
"wr;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Reference
Name "Output1"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [465, 317, 530, 333]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Output"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Output Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
SIGNALCOMPILER_PARAMS "sgn;Signed Integer;nodetype;Output Port;bwl;8;b"
"wr;0;sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator"
Ports [0, 1]
Position [60, 253, 105, 287]
PulseType "Time based"
Period "2048"
PulseWidth "50"
}
Block {
BlockType Scope
Name "Scope"
Ports [2]
Position [595, 260, 625, 295]
Floating off
Location [5, 81, 1029, 762]
Open off
NumInputPorts "2"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "-5~-5"
YMax "5~5"
DataFormat "StructureWithTime"
MaxDataPoints "50000"
SampleTime "0"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [294, 163, 363, 210]
ForegroundColor "blue"
SourceBlock "Altelink/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "Stratix"
opt "Speed"
synthtool "Others"
vstim on
SynthAct "None"
workdir "E:\\sunyu\\PGC\\dspbuild\\200651000756-99\\ASK"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation off
JTAGCable "USB-Blaster [USB-0]"
dspb_ver "5.1"
}
Block {
BlockType Reference
Name "SignalTap II Analysis"
Ports []
Position [575, 359, 625, 401]
ForegroundColor "blue"
SourceBlock "Altelink/AltLab/SignalTap II Analysis"
SourceType "SignalTapAnalyzer AlteraBlockSet"
}
Line {
SrcBlock "Increment\nDecrement"
SrcPort 1
DstBlock "LUT"
DstPort 1
}
Line {
SrcBlock "LUT"
SrcPort 1
DstBlock "Output1"
DstPort 1
}
Line {
SrcBlock "Pulse\nGenerator"
SrcPort 1
DstBlock "Input"
DstPort 1
}
Line {
SrcBlock "Input"
SrcPort 1
Points [5, 0]
Branch {
Points [0, 45]
DstBlock "Increment\nDecrement"
DstPort 1
}
Branch {
DstBlock "Output"
DstPort 1
}
}
Line {
SrcBlock "GND"
SrcPort 1
DstBlock "Increment\nDecrement"
DstPort 2
}
Line {
SrcBlock "Output1"
SrcPort 1
Points [20, 0; 0, -40]
DstBlock "Scope"
DstPort 2
}
Line {
SrcBlock "Output"
SrcPort 1
DstBlock "Scope"
DstPort 1
}
}
}
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