ask_demoden.mdl

matlab下

      ForegroundColor	      "red"
      SourceBlock	      "bus_alteradspbuilder/Input"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Single Bit"
      nodetype		      "Input Port"
      bwl		      "1"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Input"
      ppat		      "d:\\matlab6p5\\work\\ask\\DSPBuilder_ask_demode"
"n"
      nSgCpl		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "LUT"
      Ports		      [1, 1]
      Position		      [285, 230, 375, 270]
      ForegroundColor	      "red"
      SourceBlock	      "gate_alteradspbuilder/LUT"
      SourceType	      "LUT  AlteraBlockSet"
      BusType		      "Signed Integer"
      bwl		      "8"
      bwr		      "0"
      bwaddr		      "8"
      MatlabArray	      "127*sin( [0:2*pi/(2^8):2*pi] )"
      LocPin		      "ask_demodenLUT"
      lpm		      off
      modulename	      "d:\\matlab6p5\\work\\ask\\DSPBuilder_ask_demode"
"n\\ask_demodenLUT.lut"
      pipeline		      off
      IslibDir		      "0"
      clken		      off
    }
    Block {
      BlockType		      Reference
      Name		      "Logical\nBit Operator"
      Ports		      [1, 1]
      Position		      [685, 256, 755, 304]
      ForegroundColor	      "blue"
      SourceBlock	      "gate_alteradspbuilder/Logical\nBit Operator"
      SourceType	      "LogiBit AlteraBlockSet"
      Operator		      "NOT"
      Inputs		      "4"
    }
    Block {
      BlockType		      Reference
      Name		      "Output"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [775, 227, 840, 243]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Output1"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [790, 272, 855, 288]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "1"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Output2"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [745, 172, 810, 188]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/Output"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Output Port"
      bwl		      "1"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "Output"
      nSgCpl		      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Parallel \nAdder Subtractor"
      Ports		      [2, 1]
      Position		      [505, 232, 540, 308]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
      SourceType	      "Sum AlteraBlockSet"
      Inputs		      "2"
      direction		      "++"
      pipeline		      on
      clken		      off
      MaskValue		      "1"
    }
    Block {
      BlockType		      DiscretePulseGenerator
      Name		      "Pulse\nGenerator"
      Position		      [15, 173, 60, 207]
      PulseType		      "Time based"
      Period		      "2048"
      PulseWidth	      "50"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      Ports		      [3]
      Position		      [900, 172, 930, 208]
      Location		      [5, 60, 1029, 741]
      Open		      off
      NumInputPorts	      "3"
      ZoomMode		      "xonly"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
	axes3			"%<SignalLabel>"
      }
      List {
	ListType		SelectedSignals
	axes1			""
	axes2			""
	axes3			""
      }
      YMin		      "-5~-5~-5"
      YMax		      "5~5~5"
      DataFormat	      "StructureWithTime"
      MaxDataPoints	      "50000"
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [514, 43, 583, 90]
      ForegroundColor	      "blue"
      SourceBlock	      "ALTELINK/AltLab/SignalCompiler"
      SourceType	      "SignalCompiler"
      family		      "Stratix"
      opt		      "Speed"
      synthtool		      "Others"
      vstim		      on
      SynthAct		      "None"
      workdir		      "d:\\matlab6p5\\work\\ask"
      Procetype		      "prod"
      UseReset		      on
      ResetPin		      "Active High"
      ClockPin		      "Output to Pin"
      ClockPeriod	      "20"
      UseSignalTap	      off
      CreatePtfFile	      off
      SignalTapDepth	      "128"
      VerilogSupport	      off
      UniqueVHDLHierarchyName off
      RegenerateIPFunctionalModel off
      RunUpdatedSimulation    off
    }
    Line {
      SrcBlock		      "Increment\nDecrement"
      SrcPort		      1
      DstBlock		      "LUT"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Pulse\nGenerator"
      SrcPort		      1
      DstBlock		      "Input"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Input"
      SrcPort		      1
      Points		      [5, 0]
      Branch {
	Points			[0, 50]
	DstBlock		"Increment\nDecrement"
	DstPort			1
      }
      Branch {
	Points			[0, -10]
	DstBlock		"Delay2"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "GND"
      SrcPort		      1
      DstBlock		      "Increment\nDecrement"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Comparator"
      SrcPort		      1
      DstBlock		      "Logical\nBit Operator"
      DstPort		      1
    }
    Line {
      SrcBlock		      "GND1"
      SrcPort		      1
      Points		      [0, -35]
      DstBlock		      "Comparator"
      DstPort		      2
    }
    Line {
      SrcBlock		      "LUT"
      SrcPort		      1
      Points		      [15, 0]
      Branch {
	Points			[0, 40]
	DstBlock		"Delay1"
	DstPort			1
      }
      Branch {
	DstBlock		"Parallel \nAdder Subtractor"
	DstPort			1
      }
      Branch {
	Points			[0, -15]
	DstBlock		"Output"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Delay1"
      SrcPort		      1
      DstBlock		      "Parallel \nAdder Subtractor"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Parallel \nAdder Subtractor"
      SrcPort		      1
      DstBlock		      "Comparator"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Logical\nBit Operator"
      SrcPort		      1
      DstBlock		      "Output1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Delay2"
      SrcPort		      1
      DstBlock		      "Output2"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Output2"
      SrcPort		      1
      DstBlock		      "Scope"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Output1"
      SrcPort		      1
      Points		      [10, 0; 0, -80]
      DstBlock		      "Scope"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Output"
      SrcPort		      1
      Points		      [5, 0; 0, -45]
      DstBlock		      "Scope"
      DstPort		      2
    }
  }
}