📄 ask_demoden1.mdl
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LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Product"
Ports [2, 1]
Position [385, 308, 450, 357]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Product"
SourceType "Product Altera BlockSet"
pipeline "0"
lpm off
eab off
clken off
MaskValue "1"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator1"
Position [15, 213, 60, 247]
PulseType "Time based"
Period "2048"
PulseWidth "50"
}
Block {
BlockType Scope
Name "Scope1"
Ports [4]
Position [810, 147, 840, 183]
Location [5, 81, 1029, 762]
Open off
NumInputPorts "4"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
axes4 "%<SignalLabel>"
}
List {
ListType SelectedSignals
axes1 ""
axes2 ""
axes3 ""
axes4 ""
}
YMin "-5~-5~-5~-5"
YMax "5~5~5~5"
DataFormat "StructureWithTime"
MaxDataPoints "50000"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [274, 48, 343, 95]
ForegroundColor "blue"
SourceBlock "ALTELINK/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "Stratix"
opt "Speed"
synthtool "Others"
vstim on
SynthAct "None"
workdir "d:\\matlab6p5\\work\\ask"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation off
}
Block {
BlockType SubSystem
Name "Subsystem_lowpassfilter"
Ports [1, 1]
Position [510, 305, 550, 365]
TreatAsAtomicUnit off
System {
Name "Subsystem_lowpassfilter"
Location [2, 82, 1014, 722]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [25, 43, 55, 57]
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [200, 95, 245, 145]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [200, 195, 245, 245]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "Delay2"
Ports [1, 1]
Position [200, 285, 245, 335]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "Gain"
Ports [1, 1]
Position [330, 27, 390, 73]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "63"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "63"
}
Block {
BlockType Reference
Name "Gain1"
Ports [1, 1]
Position [330, 97, 390, 143]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "127"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "127"
}
Block {
BlockType Reference
Name "Gain2"
Ports [1, 1]
Position [340, 197, 400, 243]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "127"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "127"
}
Block {
BlockType Reference
Name "Gain3"
Ports [1, 1]
Position [345, 287, 405, 333]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Gain"
SourceType "Gain AlteraBlockSet"
vgain "127"
BusType "Signed Integer"
bwl "8"
bwr "0"
pipeline "0"
lpm off
clken off
MaskValue "1"
gain "127"
}
Block {
BlockType Reference
Name "Input"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [80, 42, 145, 58]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input"
ppat "d:\\matlab6p5\\work\\low_pass_filter3tap\\D"
"SPBuilder_low_pass_filter3tap"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Parallel \nAdder Subtractor"
Ports [4, 1]
Position [490, 142, 525, 218]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Parallel \nAdder Su"
"btractor"
SourceType "Sum AlteraBlockSet"
Inputs "4"
direction "++++"
pipeline on
clken off
MaskValue "1"
}
Block {
BlockType Outport
Name "Out2"
Position [550, 173, 580, 187]
}
Line {
SrcBlock "Input"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
DstBlock "Gain"
DstPort 1
}
Branch {
Points [0, 70]
DstBlock "Delay"
DstPort 1
}
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
DstBlock "Gain1"
DstPort 1
}
Branch {
Points [0, 45; -100, 0; 0, 55]
DstBlock "Delay1"
DstPort 1
}
}
Line {
SrcBlock "Delay1"
SrcPort 1
Points [0, 0; 30, 0]
Branch {
DstBlock "Gain2"
DstPort 1
}
Branch {
Points [0, 45; -125, 0; 0, 45]
DstBlock "Delay2"
DstPort 1
}
}
Line {
SrcBlock "Delay2"
SrcPort 1
DstBlock "Gain3"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [65, 0; 0, 100]
DstBlock "Parallel \nAdder Subtractor"
DstPort 1
}
Line {
SrcBlock "Gain1"
SrcPort 1
Points [30, 0; 0, 50]
DstBlock "Parallel \nAdder Subtractor"
DstPort 2
}
Line {
SrcBlock "Gain2"
SrcPort 1
Points [25, 0; 0, -30]
DstBlock "Parallel \nAdder Subtractor"
DstPort 3
}
Line {
SrcBlock "Gain3"
SrcPort 1
Points [60, 0; 0, -100]
DstBlock "Parallel \nAdder Subtractor"
DstPort 4
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Input"
DstPort 1
}
Line {
SrcBlock "Parallel \nAdder Subtractor"
SrcPort 1
DstBlock "Out2"
DstPort 1
}
}
}
Line {
SrcBlock "Increment\nDecrement2"
SrcPort 1
DstBlock "LUT2"
DstPort 1
}
Line {
SrcBlock "LUT2"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
DstBlock "Output3"
DstPort 1
}
Branch {
Points [0, 120]
DstBlock "Product"
DstPort 1
}
}
Line {
SrcBlock "Pulse\nGenerator1"
SrcPort 1
Points [0, -50; -55, 0; 0, -35]
DstBlock "Input1"
DstPort 1
}
Line {
SrcBlock "Input1"
SrcPort 1
Points [0, 0; 5, 0]
Branch {
Points [0, 45]
DstBlock "Increment\nDecrement2"
DstPort 1
}
Branch {
DstBlock "Output2"
DstPort 1
}
}
Line {
SrcBlock "GND1"
SrcPort 1
DstBlock "Increment\nDecrement2"
DstPort 2
}
Line {
SrcBlock "Output3"
SrcPort 1
Points [20, 0; 0, -40]
DstBlock "Scope1"
DstPort 2
}
Line {
SrcBlock "Output2"
SrcPort 1
Points [350, 0]
DstBlock "Scope1"
DstPort 1
}
Line {
SrcBlock "Increment\nDecrement1"
SrcPort 1
DstBlock "LUT1"
DstPort 1
}
Line {
SrcBlock "LUT1"
SrcPort 1
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "Product"
SrcPort 1
Points [5, 0; 0, -5]
Branch {
Points [0, -100; 80, 0; 0, -60]
DstBlock "Scope1"
DstPort 3
}
Branch {
Points [0, 5]
DstBlock "Subsystem_lowpassfilter"
DstPort 1
}
}
Line {
SrcBlock "Subsystem_lowpassfilter"
SrcPort 1
DstBlock "Magnitude"
DstPort 1
}
Line {
SrcBlock "Constant"
SrcPort 1
Points [40, 0]
DstBlock "Comparator"
DstPort 2
}
Line {
SrcBlock "Comparator"
SrcPort 1
DstBlock "Output"
DstPort 1
}
Line {
SrcBlock "Output"
SrcPort 1
Points [0, -165]
DstBlock "Scope1"
DstPort 4
}
Line {
SrcBlock "Magnitude"
SrcPort 1
DstBlock "Comparator"
DstPort 1
}
}
}
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