ask_modenaltblk.xml

matlab下

<ask_moden>
<dspbuilder_info>
	<dspbuilder_version>6.0</dspbuilder_version>
	<dspbuilder_build_number>Internal Build 180</dspbuilder_build_number>
	<dspbuilder_build_date>04/27/2006</dspbuilder_build_date>
	<toplevel_design_name>ask_moden</toplevel_design_name>
	<date_stamp>20061231222835</date_stamp>
</dspbuilder_info>
   <block_dspbuilder>
      <db_block>
         <instancename>Input</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>1</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SingleBit</pvalue>
            <pname>nodetype</pname>
            <pvalue>InputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>1</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>2</outportfanout>
            <dstport>1</dstport>
            <dstblk>Output</dstblk>
            <dstport>1</dstport>
            <dstblk>IncrementDecrement</dstblk>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>Output</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>2</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>OutputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>1</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Input</srcblk>
            <srcport>1</srcport>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>Output1</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>3</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>OutputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>8</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>LUT</srcblk>
            <srcport>1</srcport>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>LUT</instancename>
         <sourcename>LUTAlteraBlockSet</sourcename>
         <instancenumber>4</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>BusType</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>8</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>bwaddr</pname>
            <pvalue>8</pvalue>
            <pname>lpm</pname>
            <pvalue>off</pvalue>
            <pname>pipeline</pname>
            <pvalue>off</pvalue>
            <pname>clken</pname>
            <pvalue>off</pvalue>
            <pname>LocPin</pname>
            <pvalue>ask_modenLUT</pvalue>
            <pname>ena</pname>
            <pvalue>off</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>IncrementDecrement</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>Output1</dstblk>
         </port_db>
         <nparameter>10</nparameter>
      </db_block>
      <db_block>
         <instancename>IncrementDecrement</instancename>
         <sourcename>HDLEntityAlteraBlockSet</sourcename>
         <instancenumber>5</instancenumber>
         <inport>2</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>HDLInputPortsMappingAltera</pname>
            <pvalue>ena.1.0.b</pvalue>
            <pname>HDLOutputPortsMappingAltera</pname>
            <pvalue>result.8.0.u</pvalue>
            <pname>HDLParameterMappingAltera</pname>
            <pvalue>lpm_width.8.natural,cst_val."00000000".string,lpm.0.natural,isunsigned.1.natural,SequenceLength.1.natural,SequenceValue.1.natural,direction.0.natural</pvalue>
            <pname>HDLImplicitPortsMappingAltera</pname>
            <pvalue>clock.clock,2.sclror</pvalue>
            <pname>HDLComponentNameAltera</pname>
            <pvalue>IncDec</pvalue>
            <pname>BusType</pname>
            <pvalue>UnsignedInteger</pvalue>
            <pname>bwl</pname>
            <pvalue>8</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>clken</pname>
            <pvalue>on</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>direction</pname>
            <pvalue>Increment</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Input</srcblk>
            <srcport>1</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>GND</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>LUT</dstblk>
         </port_db>
         <nparameter>12</nparameter>
      </db_block>
      <db_block>
         <instancename>GND</instancename>
         <sourcename>SGNDAlteraBlockSet</sourcename>
         <instancenumber>6</instancenumber>
         <inport>0</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
         </parameters_db>
         <port_db>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>2</dstport>
            <dstblk>IncrementDecrement</dstblk>
         </port_db>
         <nparameter>1</nparameter>
      </db_block>
   </block_dspbuilder>
<top_sources>
	<library></library>
</top_sources>
   <top_parameters>
      <starttime>0.0</starttime>
      <stoptime>10000</stoptime>
      <fixedstep>auto</fixedstep>
      <nsubsystem>0</nsubsystem>
      <nblocks>6</nblocks>
   </top_parameters>
   <top_signalcompiler>
      <family>Stratix</family>
      <opt>Speed</opt>
      <synthtool>Others</synthtool>
      <vstim>on</vstim>
      <SynthAct>None</SynthAct>
      <workdir>E:\sunyu\PGC\dspbuild\200651000756-99\ASK</workdir>
      <Procetype>prod</Procetype>
      <UseReset>on</UseReset>
      <ResetPin>Active High</ResetPin>
      <ClockPin>Output to Pin</ClockPin>
      <ClockPeriod>20</ClockPeriod>
      <UseSignalTap>off</UseSignalTap>
      <CreatePtfFile>off</CreatePtfFile>
      <SignalTapDepth>128</SignalTapDepth>
      <VerilogSupport>off</VerilogSupport>
      <JTAGCable>USB-Blaster [USB-0]</JTAGCable>
      <bContainMegaCoreIpTb>0</bContainMegaCoreIpTb>
   </top_signalcompiler>
</ask_moden>