📄 cnt5.rpt
字号:
75 118 H OUTPUT t 0 0 0 0 0 0 0 DOUT55
77 123 H OUTPUT t 0 0 0 0 0 0 0 DOUT56
81 128 H OUTPUT t 0 0 0 0 0 0 0 DOUT57
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda\hxrjtd\cnt5.rpt
cnt5
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 121 H SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:38|addcore:adder|addcore:adder0|result_node1
- 119 H SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:38|addcore:adder|addcore:adder0|result_node2
- 116 H DFFE + t 0 0 0 2 1 3 1 CNT3B2 (:12)
- 114 H DFFE + t 0 0 0 2 1 3 2 CNT3B1 (:13)
- 113 H TFFE + t 0 0 0 2 1 1 3 CNT3B0 (:14)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda\hxrjtd\cnt5.rpt
cnt5
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------- LC125 DOUT50
| +----------------------- LC126 DOUT51
| | +--------------------- LC115 DOUT52
| | | +------------------- LC117 DOUT53
| | | | +----------------- LC120 DOUT54
| | | | | +--------------- LC118 DOUT55
| | | | | | +------------- LC123 DOUT56
| | | | | | | +----------- LC128 DOUT57
| | | | | | | | +--------- LC121 |LPM_ADD_SUB:38|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | +------- LC119 |LPM_ADD_SUB:38|addcore:adder|addcore:adder0|result_node2
| | | | | | | | | | +----- LC116 CNT3B2
| | | | | | | | | | | +--- LC114 CNT3B1
| | | | | | | | | | | | +- LC113 CNT3B0
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC121-> - - - - - - - - - - - * - | - - - - - - - * | <-- |LPM_ADD_SUB:38|addcore:adder|addcore:adder0|result_node1
LC119-> - - - - - - - - - - * - - | - - - - - - - * | <-- |LPM_ADD_SUB:38|addcore:adder|addcore:adder0|result_node2
LC116-> * * * - - - - - - * - - - | - - - - - - - * | <-- CNT3B2
LC114-> * * * - - - - - * * - - - | - - - - - - - * | <-- CNT3B1
LC113-> * - - - - - - - * * - - * | - - - - - - - * | <-- CNT3B0
Pin
83 -> - - - - - - - - - - - - - | - - - - - - - - | <-- CLK
12 -> - - - - - - - - - - * * * | - - - - - - - * | <-- EN5B
11 -> - - - - - - - - - - * * * | - - - - - - - * | <-- EN5M
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda\hxrjtd\cnt5.rpt
cnt5
** EQUATIONS **
CLK : INPUT;
EN5B : INPUT;
EN5M : INPUT;
-- Node name is ':14' = 'CNT3B0'
-- Equation name is 'CNT3B0', location is LC113, type is buried.
CNT3B0 = TFFE(!_EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = CNT3B0 & !EN5B & !EN5M;
-- Node name is ':13' = 'CNT3B1'
-- Equation name is 'CNT3B1', location is LC114, type is buried.
CNT3B1 = DFFE( _EQ002 $ _LC121, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = !EN5B & !EN5M & !_LC121;
-- Node name is ':12' = 'CNT3B2'
-- Equation name is 'CNT3B2', location is LC116, type is buried.
CNT3B2 = DFFE( _EQ003 $ _LC119, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !EN5B & !EN5M & !_LC119;
-- Node name is 'DOUT50'
-- Equation name is 'DOUT50', location is LC125, type is output.
DOUT50 = LCELL( _EQ004 $ !CNT3B0);
_EQ004 = !CNT3B0 & CNT3B1 & CNT3B2;
-- Node name is 'DOUT51'
-- Equation name is 'DOUT51', location is LC126, type is output.
DOUT51 = LCELL( _EQ005 $ CNT3B1);
_EQ005 = CNT3B1 & CNT3B2;
-- Node name is 'DOUT52'
-- Equation name is 'DOUT52', location is LC115, type is output.
DOUT52 = LCELL( _EQ006 $ !CNT3B2);
_EQ006 = CNT3B1 & !CNT3B2;
-- Node name is 'DOUT53'
-- Equation name is 'DOUT53', location is LC117, type is output.
DOUT53 = LCELL( VCC $ VCC);
-- Node name is 'DOUT54'
-- Equation name is 'DOUT54', location is LC120, type is output.
DOUT54 = LCELL( VCC $ VCC);
-- Node name is 'DOUT55'
-- Equation name is 'DOUT55', location is LC118, type is output.
DOUT55 = LCELL( VCC $ VCC);
-- Node name is 'DOUT56'
-- Equation name is 'DOUT56', location is LC123, type is output.
DOUT56 = LCELL( VCC $ VCC);
-- Node name is 'DOUT57'
-- Equation name is 'DOUT57', location is LC128, type is output.
DOUT57 = LCELL( VCC $ VCC);
-- Node name is '|LPM_ADD_SUB:38|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC121', type is buried
_LC121 = LCELL( CNT3B1 $ CNT3B0);
-- Node name is '|LPM_ADD_SUB:38|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC119', type is buried
_LC119 = LCELL( CNT3B2 $ _EQ007);
_EQ007 = CNT3B0 & CNT3B1;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\eda\hxrjtd\cnt5.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,576K
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