📄 hxrjtd.map.rpt
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Analysis & Synthesis report for HXRJTD compilation.
Wed May 24 16:39:37 2006
Version 3.0 Build 199 06/26/2003 SJ Full Version
Command: quartus_map --import_settings_files=on --export_settings_files=off hxrjtd -c HXRJTD
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; Table of Contents ;
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1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Elapsed Time
5. Analysis & Synthesis Summary
6. Analysis & Synthesis Settings
7. Hierarchy
8. State Machine - jtdkz:5|STATE
9. Analysis & Synthesis Resource Utilization by Entity
10. Analysis & Synthesis Equations
11. Analysis & Synthesis Messages
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; Legal Notice ;
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Copyright (C) 1991-2003 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
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; Flow Summary ;
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; Flow Status ; Successful - Wed May 24 16:39:37 2006 ;
; Compiler Setting Name ; HXRJTD ;
; Top-level Entity Name ; nn ;
; Family ; APEX20KE ;
; Device ; EP20K300EQC240-3 ;
; Total logic elements ; 135 ;
; Total pins ; 26 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
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; Flow Settings ;
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; Option ; Setting ;
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; Start date & time ; 05/24/2006 16:39:33 ;
; Main task ; Compilation ;
; Compiler Setting Name ; HXRJTD ;
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; Flow Elapsed Time ;
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; Module Name ; Elapsed Time ;
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; Analysis & Synthesis ; 00:00:04 ;
; Total ; 00:00:04 ;
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; Analysis & Synthesis Summary ;
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; Analysis & Synthesis Status ; Successful - Wed May 24 16:39:37 2006 ;
; Compiler Setting Name ; HXRJTD ;
; Top-level Entity Name ; nn ;
; Family ; APEX20KE ;
; Total logic elements ; 135 ;
; Total pins ; 26 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
-----------------------------------------------------------------------
------------------------------------------------------------
; Analysis & Synthesis Settings ;
------------------------------------------------------------
; Option ; Setting ;
------------------------------------------------------------
; Use Generated Physical Constraints File ; On ;
; Physical Synthesis Level for Resynthesis ; Normal ;
; Resynthesis Optimization Effort ; Normal ;
; Type of Retiming Performed During Resynthesis ; Full ;
; Perform gate-level register retiming ; Off ;
; Perform WYSIWYG primitive resynthesis ; Off ;
; Focus entity name ; |nn ;
; Family name ; APEX20KE ;
; Preserve fewer node names ; On ;
; Disk space/compilation speed tradeoff ; Normal ;
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--------------
; Hierarchy ;
--------------
Hierarchy
nn
cnt15:1
lpm_counter:CNT5B_rtl_7
alt_synch_counter:wysi_counter
cnt25:2
lpm_counter:CNTB_rtl_9
alt_synch_counter:wysi_counter
cnt5:3
lpm_counter:CNT3B_rtl_8
alt_synch_counter:wysi_counter
fpj:4
jtdkz:5
xskz:6
---------------------------------------------------
; State Machine - jtdkz:5|STATE ;
---------------------------------------------------
; Name ; STATE~7 ; STATE~6 ; STATE~5 ; STATE~4 ;
---------------------------------------------------
; STATE.a ; 0 ; 0 ; 0 ; 0 ;
; STATE.b ; 0 ; 0 ; 1 ; 1 ;
; STATE.c ; 0 ; 1 ; 0 ; 1 ;
; STATE.d ; 1 ; 0 ; 0 ; 1 ;
---------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Analysis & Synthesis Resource Utilization by Entity ;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node ; Logic Cells ; Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; |nn ; 135 (0) ; 28 ; 0 ; 26 ; 0 ; 107 (0) ; 5 (0) ; 23 (0) ; |nn ;
; |cnt15:1| ; 11 (5) ; 4 ; 0 ; 0 ; 0 ; 7 (5) ; 0 (0) ; 4 (0) ; |nn|cnt15:1 ;
; |lpm_counter:CNT5B_rtl_7| ; 6 (0) ; 4 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 4 (0) ; |nn|cnt15:1|lpm_counter:CNT5B_rtl_7 ;
; |alt_synch_counter:wysi_counter| ; 6 (6) ; 4 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |nn|cnt15:1|lpm_counter:CNT5B_rtl_7|alt_synch_counter:wysi_counter ;
; |cnt25:2| ; 23 (15) ; 5 ; 0 ; 0 ; 0 ; 18 (15) ; 0 (0) ; 5 (0) ; |nn|cnt25:2 ;
; |lpm_counter:CNTB_rtl_9| ; 8 (0) ; 5 ; 0 ; 0 ; 0 ; 3 (0) ; 0 (0) ; 5 (0) ; |nn|cnt25:2|lpm_counter:CNTB_rtl_9 ;
; |alt_synch_counter:wysi_counter| ; 8 (8) ; 5 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 5 (5) ; |nn|cnt25:2|lpm_counter:CNTB_rtl_9|alt_synch_counter:wysi_counter ;
; |cnt5:3| ; 7 (1) ; 3 ; 0 ; 0 ; 0 ; 4 (1) ; 0 (0) ; 3 (0) ; |nn|cnt5:3 ;
; |lpm_counter:CNT3B_rtl_8| ; 6 (0) ; 3 ; 0 ; 0 ; 0 ; 3 (0) ; 0 (0) ; 3 (0) ; |nn|cnt5:3|lpm_counter:CNT3B_rtl_8 ;
; |alt_synch_counter:wysi_counter| ; 6 (6) ; 3 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 3 (3) ; |nn|cnt5:3|lpm_counter:CNT3B_rtl_8|alt_synch_counter:wysi_counter ;
; |fpj:4| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; |nn|fpj:4 ;
; |jtdkz:5| ; 35 (35) ; 15 ; 0 ; 0 ; 0 ; 20 (20) ; 4 (4) ; 11 (11) ; |nn|jtdkz:5 ;
; |xskz:6| ; 58 (58) ; 0 ; 0 ; 0 ; 0 ; 58 (58) ; 0 (0) ; 0 (0) ; |nn|xskz:6 ;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------
; Analysis & Synthesis Equations ;
-----------------------------------
The equations can be found in E:\HXRJTD\HXRJTD.map.eqn.
----------------------------------
; Analysis & Synthesis Messages ;
----------------------------------
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 3.0 Build 199 06/26/2003 SJ Full Version
Info: Processing started: Wed May 24 16:39:32 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off hxrjtd -c HXRJTD
Info: Found 2 design units and 1 entities in source file E:\HXRJTD\cnt15.vhd
Info: Found design unit 1: cnt15-one
Info: Found entity 1: cnt15
Info: Found 2 design units and 1 entities in source file E:\HXRJTD\cnt25.vhd
Info: Found design unit 1: cnt25-one
Info: Found entity 1: cnt25
Info: Found 2 design units and 1 entities in source file E:\HXRJTD\cnt5.vhd
Info: Found design unit 1: cnt5-one
Info: Found entity 1: cnt5
Info: Found 2 design units and 1 entities in source file E:\HXRJTD\fpj.vhd
Info: Found design unit 1: fpj-one
Info: Found entity 1: fpj
Info: Found 2 design units and 1 entities in source file E:\HXRJTD\jtdkz.vhd
Info: Found design unit 1: jtdkz-one
Info: Found entity 1: jtdkz
Info: Found 1 design units and 1 entities in source file E:\HXRJTD\nn.gdf
Info: Found entity 1: nn
Info: Found 2 design units and 1 entities in source file E:\HXRJTD\xskz.vhd
Info: Found design unit 1: xskz-one
Info: Found entity 1: xskz
Info: Inferred 3 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: cnt15:1|CNT5B_rtl_7
Info: Inferred lpm_counter megafunction (LPM_WIDTH=3) from the following logic: cnt5:3|CNT3B_rtl_8
Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: cnt25:2|CNTB_rtl_9
Info: Found 1 design units and 1 entities in source file c:\quartus\libraries\megafunctions\lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file c:\quartus\libraries\megafunctions\alt_synch_counter.tdf
Info: Found entity 1: alt_synch_counter
Info: State machine |nn|jtdkz:5|STATE contains 4 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine |nn|jtdkz:5|STATE
Info: Encoding result for state machine |nn|jtdkz:5|STATE
Info: Completed encoding using 4 state bits
Info: Encoded state bit jtdkz:5|STATE~7
Info: Encoded state bit jtdkz:5|STATE~6
Info: Encoded state bit jtdkz:5|STATE~5
Info: Encoded state bit jtdkz:5|STATE~4
Info: State |nn|jtdkz:5|STATE.a uses code string 0000
Info: State |nn|jtdkz:5|STATE.b uses code string 0011
Info: State |nn|jtdkz:5|STATE.c uses code string 0101
Info: State |nn|jtdkz:5|STATE.d uses code string 1001
Info: Duplicate registers merged to single register
Info: Duplicate register jtdkz:5|BR~reg0 merged to single register jtdkz:5|MR~reg0, power-up level changed
Warning: Output pins are stuck at VCC or GND
Warning: Pin DOUTB[7] stuck at GND
Warning: Pin DOUTB[6] stuck at GND
Warning: Pin DOUTM[7] stuck at GND
Warning: Pin DOUTM[6] stuck at GND
Info: Implemented 161 device resources after synthesis - the final resource count might be different
Info: Implemented 4 input pins
Info: Implemented 22 output pins
Info: Implemented 135 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Processing ended: Wed May 24 16:39:37 2006
Info: Elapsed time: 00:00:04
Info: Writing report file HXRJTD.map.rpt
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