📄 cnt15.rpt
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LC | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
83 -> - | - - - - - - - - | <-- CLK
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda\hxrjtd\cnt15.rpt
cnt15
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+------------- LC105 DOUT15B2
| +----------- LC104 DOUT15B3
| | +--------- LC101 DOUT15B4
| | | +------- LC99 DOUT15B5
| | | | +----- LC97 DOUT15B6
| | | | | +--- LC107 DOUT15B7
| | | | | | +- LC109 DOUT15M6
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'G'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
83 -> - - - - - - - | - - - - - - - - | <-- CLK
LC114-> * * * - - - - | - - - - - - * * | <-- CNT5B3
LC116-> * * * - - - - | - - - - - - * * | <-- CNT5B2
LC113-> * * * - - - - | - - - - - - * * | <-- CNT5B1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda\hxrjtd\cnt15.rpt
cnt15
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+--------------------------- LC115 DOUT15B0
| +------------------------- LC123 DOUT15B1
| | +----------------------- LC117 DOUT15M0
| | | +--------------------- LC118 DOUT15M1
| | | | +------------------- LC120 DOUT15M2
| | | | | +----------------- LC128 DOUT15M3
| | | | | | +--------------- LC126 DOUT15M4
| | | | | | | +------------- LC125 DOUT15M5
| | | | | | | | +----------- LC122 |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | +--------- LC121 |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node2
| | | | | | | | | | +------- LC119 |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | | +----- LC114 CNT5B3
| | | | | | | | | | | | +--- LC116 CNT5B2
| | | | | | | | | | | | | +- LC113 CNT5B1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC115-> * - * * * * * * * * * - - - | - - - - - - - * | <-- DOUT15B0
LC122-> - - - - - - - - - - - - - * | - - - - - - - * | <-- |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node1
LC121-> - - - - - - - - - - - - * - | - - - - - - - * | <-- |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node2
LC119-> - - - - - - - - - - - * - - | - - - - - - - * | <-- |LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node3
LC114-> - * * * * * * * - - * - - - | - - - - - - * * | <-- CNT5B3
LC116-> - * * * * * * * - * * - - - | - - - - - - * * | <-- CNT5B2
LC113-> - * * * * * * * * * * - - - | - - - - - - * * | <-- CNT5B1
Pin
83 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- CLK
12 -> * - - - - - - - - - - * * * | - - - - - - - * | <-- EN15
10 -> * - - - - - - - - - - * * * | - - - - - - - * | <-- SB
11 -> * - - - - - - - - - - * * * | - - - - - - - * | <-- SM
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda\hxrjtd\cnt15.rpt
cnt15
** EQUATIONS **
CLK : INPUT;
EN15 : INPUT;
SB : INPUT;
SM : INPUT;
-- Node name is ':23' = 'CNT5B1'
-- Equation name is 'CNT5B1', location is LC113, type is buried.
CNT5B1 = DFFE( _EQ001 $ GND, GLOBAL( CLK), VCC, !_EQ002, VCC);
_EQ001 = EN15 & _LC122
# !EN15;
_EQ002 = _X001;
_X001 = EXP( SB & SM);
-- Node name is ':22' = 'CNT5B2'
-- Equation name is 'CNT5B2', location is LC116, type is buried.
CNT5B2 = DFFE( _EQ003 $ GND, GLOBAL( CLK), VCC, !_EQ004, VCC);
_EQ003 = EN15 & _LC121
# !EN15;
_EQ004 = _X001;
_X001 = EXP( SB & SM);
-- Node name is ':21' = 'CNT5B3'
-- Equation name is 'CNT5B3', location is LC114, type is buried.
CNT5B3 = DFFE( _EQ005 $ GND, GLOBAL( CLK), VCC, !_EQ006, VCC);
_EQ005 = EN15 & _LC119
# !EN15;
_EQ006 = _X001;
_X001 = EXP( SB & SM);
-- Node name is 'DOUT15B0' = 'CNT5B0'
-- Equation name is 'DOUT15B0', location is LC115, type is output.
DOUT15B0 = CNT5B0~NOT;
CNT5B0~NOT = DFFE( EN15 $ _EQ007, GLOBAL( CLK), !_EQ008, VCC, VCC);
_EQ007 = DOUT15B0 & EN15;
_EQ008 = _X001;
_X001 = EXP( SB & SM);
-- Node name is 'DOUT15B1'
-- Equation name is 'DOUT15B1', location is LC123, type is output.
DOUT15B1 = LCELL( _EQ009 $ !CNT5B1);
_EQ009 = CNT5B1 & !CNT5B2 & !CNT5B3
# !CNT5B1 & !CNT5B3;
-- Node name is 'DOUT15B2'
-- Equation name is 'DOUT15B2', location is LC105, type is output.
DOUT15B2 = LCELL( _EQ010 $ !CNT5B2);
_EQ010 = CNT5B1 & !CNT5B2 & !CNT5B3;
-- Node name is 'DOUT15B3'
-- Equation name is 'DOUT15B3', location is LC104, type is output.
DOUT15B3 = LCELL( _EQ011 $ GND);
_EQ011 = CNT5B1 & CNT5B2 & !CNT5B3;
-- Node name is 'DOUT15B4'
-- Equation name is 'DOUT15B4', location is LC101, type is output.
DOUT15B4 = LCELL( _EQ012 $ !CNT5B3);
_EQ012 = CNT5B1 & CNT5B2 & !CNT5B3;
-- Node name is 'DOUT15B5'
-- Equation name is 'DOUT15B5', location is LC099, type is output.
DOUT15B5 = LCELL( VCC $ VCC);
-- Node name is 'DOUT15B6'
-- Equation name is 'DOUT15B6', location is LC097, type is output.
DOUT15B6 = LCELL( VCC $ VCC);
-- Node name is 'DOUT15B7'
-- Equation name is 'DOUT15B7', location is LC107, type is output.
DOUT15B7 = LCELL( VCC $ VCC);
-- Node name is 'DOUT15M0'
-- Equation name is 'DOUT15M0', location is LC117, type is output.
DOUT15M0 = LCELL( _EQ013 $ !DOUT15B0);
_EQ013 = CNT5B1 & CNT5B2 & CNT5B3;
-- Node name is 'DOUT15M1'
-- Equation name is 'DOUT15M1', location is LC118, type is output.
DOUT15M1 = LCELL( _EQ014 $ GND);
_EQ014 = !CNT5B1 & CNT5B2 & CNT5B3 & !DOUT15B0
# !CNT5B1 & !CNT5B2 & CNT5B3 & DOUT15B0
# !CNT5B1 & CNT5B2 & !CNT5B3 & DOUT15B0
# CNT5B1 & !CNT5B3 & !DOUT15B0;
-- Node name is 'DOUT15M2'
-- Equation name is 'DOUT15M2', location is LC120, type is output.
DOUT15M2 = LCELL( _EQ015 $ CNT5B2);
_EQ015 = CNT5B1 & !CNT5B2 & !CNT5B3 & !DOUT15B0
# !CNT5B1 & CNT5B2 & CNT5B3 & DOUT15B0
# CNT5B1 & CNT5B2 & !DOUT15B0;
-- Node name is 'DOUT15M3'
-- Equation name is 'DOUT15M3', location is LC128, type is output.
DOUT15M3 = LCELL( _EQ016 $ GND);
_EQ016 = CNT5B1 & !CNT5B2 & CNT5B3 & !DOUT15B0
# !CNT5B1 & CNT5B2 & CNT5B3 & DOUT15B0
# CNT5B1 & !CNT5B2 & !CNT5B3 & DOUT15B0
# !CNT5B1 & !CNT5B2 & !CNT5B3 & !DOUT15B0;
-- Node name is 'DOUT15M4'
-- Equation name is 'DOUT15M4', location is LC126, type is output.
DOUT15M4 = LCELL( _EQ017 $ VCC);
_EQ017 = !CNT5B1 & !CNT5B2 & !CNT5B3 & DOUT15B0
# CNT5B1 & CNT5B3 & !DOUT15B0
# CNT5B2 & CNT5B3;
-- Node name is 'DOUT15M5'
-- Equation name is 'DOUT15M5', location is LC125, type is output.
DOUT15M5 = LCELL( _EQ018 $ GND);
_EQ018 = !CNT5B1 & !CNT5B2 & !CNT5B3 & DOUT15B0;
-- Node name is 'DOUT15M6'
-- Equation name is 'DOUT15M6', location is LC109, type is output.
DOUT15M6 = LCELL( VCC $ VCC);
-- Node name is 'DOUT15M7'
-- Equation name is 'DOUT15M7', location is LC083, type is output.
DOUT15M7 = LCELL( VCC $ VCC);
-- Node name is '|LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC122', type is buried
_LC122 = LCELL( CNT5B1 $ !DOUT15B0);
-- Node name is '|LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC121', type is buried
_LC121 = LCELL( CNT5B2 $ _EQ019);
_EQ019 = CNT5B1 & !DOUT15B0;
-- Node name is '|LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC119', type is buried
_LC119 = LCELL( CNT5B3 $ _EQ020);
_EQ020 = CNT5B1 & CNT5B2 & !DOUT15B0;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\eda\hxrjtd\cnt15.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,760K
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