📄 cnt25.rpt
字号:
| | | | | | | that feed LAB 'G'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
83 -> - - - - - - - | - - - - - - - - | <-- CLK
LC113-> * - - * * * * | - - - - - - * * | <-- CNTB4
LC114-> * - - * * * * | - - - - - - * * | <-- CNTB3
LC119-> * - - * * * * | - - - - - - * * | <-- CNTB2
LC116-> * - - * * * * | - - - - - - * * | <-- CNTB1
LC117-> * - - - - - - | - - - - - - * * | <-- CNTB0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda\hxrjtd\cnt25.rpt
cnt25
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------------- LC115 DOUT25B0
| +----------------------------- LC126 DOUT25B2
| | +--------------------------- LC125 DOUT25B3
| | | +------------------------- LC123 DOUT25B4
| | | | +----------------------- LC120 DOUT25B5
| | | | | +--------------------- LC128 DOUT25M0
| | | | | | +------------------- LC118 DOUT25M1
| | | | | | | +----------------- LC124 |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node1
| | | | | | | | +--------------- LC127 |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node2
| | | | | | | | | +------------- LC122 |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | +----------- LC121 |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node4
| | | | | | | | | | | +--------- LC113 CNTB4
| | | | | | | | | | | | +------- LC114 CNTB3
| | | | | | | | | | | | | +----- LC119 CNTB2
| | | | | | | | | | | | | | +--- LC116 CNTB1
| | | | | | | | | | | | | | | +- LC117 CNTB0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC124-> - - - - - - - - - - - - - - * - | - - - - - - - * | <-- |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node1
LC127-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node2
LC122-> - - - - - - - - - - - - * - - - | - - - - - - - * | <-- |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node3
LC121-> - - - - - - - - - - - * - - - - | - - - - - - - * | <-- |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node4
LC113-> * * * * * * * - - - * - - - - - | - - - - - - * * | <-- CNTB4
LC114-> * * * * * * * - - * * - - - - - | - - - - - - * * | <-- CNTB3
LC119-> * * * * * * * - * * * - - - - - | - - - - - - * * | <-- CNTB2
LC116-> * * * * * * * * * * * - - - - - | - - - - - - * * | <-- CNTB1
LC117-> * * * * * * - * * * * - - - - * | - - - - - - * * | <-- CNTB0
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- CLK
11 -> - - - - - - - - - - - * * * * * | - - - - - - - * | <-- EN25
12 -> - - - - - - - - - - - * * * * * | - - - - - - - * | <-- SB
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda\hxrjtd\cnt25.rpt
cnt25
** EQUATIONS **
CLK : INPUT;
EN25 : INPUT;
SB : INPUT;
-- Node name is ':24' = 'CNTB0'
-- Equation name is 'CNTB0', location is LC117, type is buried.
CNTB0 = DFFE( _EQ001 $ !EN25, GLOBAL( CLK), VCC, SB, VCC);
_EQ001 = !CNTB0 & EN25;
-- Node name is ':23' = 'CNTB1'
-- Equation name is 'CNTB1', location is LC116, type is buried.
CNTB1 = DFFE( _EQ002 $ GND, GLOBAL( CLK), VCC, SB, VCC);
_EQ002 = EN25 & _LC124
# !EN25;
-- Node name is ':22' = 'CNTB2'
-- Equation name is 'CNTB2', location is LC119, type is buried.
CNTB2 = DFFE( _EQ003 $ GND, GLOBAL( CLK), VCC, SB, VCC);
_EQ003 = EN25 & _LC127
# !EN25;
-- Node name is ':21' = 'CNTB3'
-- Equation name is 'CNTB3', location is LC114, type is buried.
CNTB3 = DFFE( _EQ004 $ GND, GLOBAL( CLK), VCC, SB, VCC);
_EQ004 = EN25 & _LC122
# !EN25;
-- Node name is ':20' = 'CNTB4'
-- Equation name is 'CNTB4', location is LC113, type is buried.
CNTB4 = DFFE( _EQ005 $ GND, GLOBAL( CLK), VCC, SB, VCC);
_EQ005 = EN25 & _LC121
# !EN25;
-- Node name is 'DOUT25B0'
-- Equation name is 'DOUT25B0', location is LC115, type is output.
DOUT25B0 = LCELL( _EQ006 $ !CNTB4);
_EQ006 = !CNTB0 & !CNTB1 & !CNTB2 & CNTB3 & CNTB4
# CNTB0 & !CNTB3 & CNTB4
# !CNTB0 & !CNTB4;
-- Node name is 'DOUT25B1'
-- Equation name is 'DOUT25B1', location is LC109, type is output.
DOUT25B1 = LCELL( _EQ007 $ _EQ008);
_EQ007 = CNTB0 & CNTB1 & !CNTB2 & CNTB4 & _X001 & _X002 & _X003 &
_X004 & _X005 & _X006
# CNTB0 & !CNTB1 & CNTB2 & !CNTB3 & _X001 & _X002 & _X003 &
_X004 & _X005 & _X006
# !CNTB0 & CNTB1 & CNTB2 & !CNTB3 & _X001 & _X002 & _X003 &
_X004 & _X005 & _X006
# !CNTB0 & !CNTB1 & CNTB2 & CNTB3 & _X001 & _X002 & _X003 &
_X004 & _X005 & _X006;
_X001 = EXP( CNTB3 & CNTB4);
_X002 = EXP(!CNTB0 & !CNTB1 & !CNTB2 & !CNTB3);
_X003 = EXP(!CNTB0 & CNTB1 & !CNTB2 & !CNTB4);
_X004 = EXP( CNTB0 & !CNTB1 & !CNTB2 & !CNTB4);
_X005 = EXP( CNTB0 & CNTB1 & CNTB3);
_X006 = EXP(!CNTB0 & CNTB2 & CNTB4);
_EQ008 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006;
_X001 = EXP( CNTB3 & CNTB4);
_X002 = EXP(!CNTB0 & !CNTB1 & !CNTB2 & !CNTB3);
_X003 = EXP(!CNTB0 & CNTB1 & !CNTB2 & !CNTB4);
_X004 = EXP( CNTB0 & !CNTB1 & !CNTB2 & !CNTB4);
_X005 = EXP( CNTB0 & CNTB1 & CNTB3);
_X006 = EXP(!CNTB0 & CNTB2 & CNTB4);
-- Node name is 'DOUT25B2'
-- Equation name is 'DOUT25B2', location is LC126, type is output.
DOUT25B2 = LCELL( _EQ009 $ _EQ010);
_EQ009 = CNTB0 & CNTB1 & CNTB2 & !CNTB3 & !CNTB4
# CNTB0 & !CNTB2 & _X007
# !CNTB0 & !CNTB2 & !CNTB4;
_X007 = EXP( CNTB1 & !CNTB3 & !CNTB4);
_EQ010 = _X008 & _X009 & _X010 & _X011;
_X008 = EXP( CNTB2 & CNTB3 & CNTB4);
_X009 = EXP(!CNTB0 & !CNTB1 & CNTB2 & CNTB3);
_X010 = EXP(!CNTB1 & CNTB2 & CNTB4);
_X011 = EXP(!CNTB0 & CNTB1 & CNTB4);
-- Node name is 'DOUT25B3'
-- Equation name is 'DOUT25B3', location is LC125, type is output.
DOUT25B3 = LCELL( _EQ011 $ _EQ012);
_EQ011 = CNTB0 & CNTB1 & !CNTB3 & _X001 & _X012 & _X013 & _X014
# CNTB1 & CNTB2 & !CNTB4 & _X001 & _X012 & _X013 & _X014
# CNTB0 & CNTB2 & !CNTB4 & _X001 & _X012 & _X013 & _X014
# CNTB0 & !CNTB1 & CNTB3 & _X001 & _X012 & _X013 & _X014;
_X001 = EXP( CNTB3 & CNTB4);
_X012 = EXP(!CNTB0 & !CNTB1 & !CNTB3);
_X013 = EXP(!CNTB0 & !CNTB2 & CNTB3);
_X014 = EXP(!CNTB2 & CNTB4);
_EQ012 = _X001 & _X012 & _X013 & _X014;
_X001 = EXP( CNTB3 & CNTB4);
_X012 = EXP(!CNTB0 & !CNTB1 & !CNTB3);
_X013 = EXP(!CNTB0 & !CNTB2 & CNTB3);
_X014 = EXP(!CNTB2 & CNTB4);
-- Node name is 'DOUT25B4'
-- Equation name is 'DOUT25B4', location is LC123, type is output.
DOUT25B4 = LCELL( _EQ013 $ GND);
_EQ013 = CNTB0 & CNTB1 & CNTB3 & !CNTB4
# !CNTB0 & !CNTB1 & !CNTB3 & CNTB4
# !CNTB0 & !CNTB1 & !CNTB2 & !CNTB3
# CNTB2 & CNTB3 & !CNTB4
# !CNTB2 & !CNTB3 & CNTB4;
-- Node name is 'DOUT25B5'
-- Equation name is 'DOUT25B5', location is LC120, type is output.
DOUT25B5 = LCELL( _EQ014 $ !CNTB4);
_EQ014 = CNTB0 & CNTB1 & CNTB3 & !CNTB4
# CNTB2 & CNTB3 & !CNTB4;
-- Node name is 'DOUT25B6'
-- Equation name is 'DOUT25B6', location is LC099, type is output.
DOUT25B6 = LCELL( VCC $ VCC);
-- Node name is 'DOUT25B7'
-- Equation name is 'DOUT25B7', location is LC097, type is output.
DOUT25B7 = LCELL( VCC $ VCC);
-- Node name is 'DOUT25M0'
-- Equation name is 'DOUT25M0', location is LC128, type is output.
DOUT25M0 = LCELL( _EQ015 $ !CNTB0);
_EQ015 = !CNTB0 & CNTB1 & CNTB3 & CNTB4
# !CNTB0 & CNTB2 & CNTB3 & CNTB4;
-- Node name is 'DOUT25M1'
-- Equation name is 'DOUT25M1', location is LC118, type is output.
DOUT25M1 = LCELL( _EQ016 $ !CNTB3);
_EQ016 = CNTB1 & CNTB2 & !CNTB3 & !CNTB4
# !CNTB1 & CNTB3 & !CNTB4
# !CNTB1 & !CNTB3;
-- Node name is 'DOUT25M2'
-- Equation name is 'DOUT25M2', location is LC101, type is output.
DOUT25M2 = LCELL( _EQ017 $ !CNTB2);
_EQ017 = !CNTB1 & CNTB2 & !CNTB3 & CNTB4
# CNTB1 & !CNTB2 & !CNTB3 & !CNTB4
# !CNTB2 & CNTB3 & CNTB4
# !CNTB1 & !CNTB2 & CNTB4;
-- Node name is 'DOUT25M3'
-- Equation name is 'DOUT25M3', location is LC104, type is output.
DOUT25M3 = LCELL( _EQ018 $ GND);
_EQ018 = CNTB1 & CNTB2 & !CNTB3 & !CNTB4
# !CNTB1 & !CNTB2 & !CNTB3 & CNTB4;
-- Node name is 'DOUT25M4'
-- Equation name is 'DOUT25M4', location is LC107, type is output.
DOUT25M4 = LCELL( _EQ019 $ !CNTB4);
_EQ019 = !CNTB1 & !CNTB3 & !CNTB4
# !CNTB2 & !CNTB3 & !CNTB4;
-- Node name is 'DOUT25M5'
-- Equation name is 'DOUT25M5', location is LC105, type is output.
DOUT25M5 = LCELL( _EQ020 $ !CNTB4);
_EQ020 = CNTB1 & CNTB2 & !CNTB4
# CNTB3 & !CNTB4;
-- Node name is 'DOUT25M6'
-- Equation name is 'DOUT25M6', location is LC085, type is output.
DOUT25M6 = LCELL( VCC $ VCC);
-- Node name is 'DOUT25M7'
-- Equation name is 'DOUT25M7', location is LC083, type is output.
DOUT25M7 = LCELL( VCC $ VCC);
-- Node name is '|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC124', type is buried
_LC124 = LCELL( CNTB1 $ CNTB0);
-- Node name is '|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC127', type is buried
_LC127 = LCELL( CNTB2 $ _EQ021);
_EQ021 = CNTB0 & CNTB1;
-- Node name is '|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC122', type is buried
_LC122 = LCELL( CNTB3 $ _EQ022);
_EQ022 = CNTB0 & CNTB1 & CNTB2;
-- Node name is '|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC121', type is buried
_LC121 = LCELL( CNTB4 $ _EQ023);
_EQ023 = CNTB0 & CNTB1 & CNTB2 & CNTB3;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs G, H
Project Information d:\eda\hxrjtd\cnt25.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,350K
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