📄 cnt25.rpt
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Project Information d:\eda\hxrjtd\cnt25.rpt
MAX+plus II Compiler Report File
Version 10.12 09/21/2001
Compiled: 06/07/2006 22:47:59
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
CNT25
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
cnt25 EPM7128SLC84-15 3 16 0 25 15 19 %
User Pins: 3 16 0
Project Information d:\eda\hxrjtd\cnt25.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'DOUT25M7' is stuck at GND
Warning: Primitive 'DOUT25M6' is stuck at GND
Warning: Primitive 'DOUT25B7' is stuck at GND
Warning: Primitive 'DOUT25B6' is stuck at GND
Project Information d:\eda\hxrjtd\cnt25.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CLK' chosen for auto global Clock
Project Information d:\eda\hxrjtd\cnt25.rpt
** FILE HIERARCHY **
|lpm_add_sub:75|
|lpm_add_sub:75|addcore:adder|
|lpm_add_sub:75|addcore:adder|addcore:adder0|
|lpm_add_sub:75|altshift:result_ext_latency_ffs|
|lpm_add_sub:75|altshift:carry_ext_latency_ffs|
|lpm_add_sub:75|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:76|
|lpm_add_sub:76|addcore:adder|
|lpm_add_sub:76|addcore:adder|addcore:adder0|
|lpm_add_sub:76|altshift:result_ext_latency_ffs|
|lpm_add_sub:76|altshift:carry_ext_latency_ffs|
|lpm_add_sub:76|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:109|
|lpm_add_sub:109|addcore:adder|
|lpm_add_sub:109|addcore:adder|addcore:adder0|
|lpm_add_sub:109|altshift:result_ext_latency_ffs|
|lpm_add_sub:109|altshift:carry_ext_latency_ffs|
|lpm_add_sub:109|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:151|
|lpm_add_sub:151|addcore:adder|
|lpm_add_sub:151|addcore:adder|addcore:adder0|
|lpm_add_sub:151|altshift:result_ext_latency_ffs|
|lpm_add_sub:151|altshift:carry_ext_latency_ffs|
|lpm_add_sub:151|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:152|
|lpm_add_sub:152|addcore:adder|
|lpm_add_sub:152|addcore:adder|addcore:adder0|
|lpm_add_sub:152|altshift:result_ext_latency_ffs|
|lpm_add_sub:152|altshift:carry_ext_latency_ffs|
|lpm_add_sub:152|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\eda\hxrjtd\cnt25.rpt
cnt25
***** Logic for device 'cnt25' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R D D D D D D
E E E E E E O O O O O O
S S S S S S V U U U U U U
E E E E E E C T T T V T T T
E R R R R R R C 2 2 2 C 2 2 2
N V V V G V V V I G G G C G 5 5 5 C 5 5 5
2 E E E N E E E N N N N L N M B B I B B M
5 D D D D D D D T D D D K D 0 2 3 O 4 5 1
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
SB | 12 74 | RESERVED
VCCIO | 13 73 | DOUT25B0
#TDI | 14 72 | GND
RESERVED | 15 71 | #TDO
RESERVED | 16 70 | DOUT25B1
RESERVED | 17 69 | DOUT25M4
RESERVED | 18 68 | DOUT25M5
GND | 19 67 | DOUT25M3
RESERVED | 20 66 | VCCIO
RESERVED | 21 65 | DOUT25M2
RESERVED | 22 EPM7128SLC84-15 64 | DOUT25B6
#TMS | 23 63 | DOUT25B7
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
RESERVED | 27 59 | GND
RESERVED | 28 58 | RESERVED
RESERVED | 29 57 | RESERVED
RESERVED | 30 56 | RESERVED
RESERVED | 31 55 | DOUT25M6
GND | 32 54 | DOUT25M7
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R R R V R R R G V R R R G R R R R R V
E E E E E C E E E N C E E E N E E E E E C
S S S S S C S S S D C S S S D S S S S S C
E E E E E I E E E I E E E E E E E E I
R R R R R O R R R N R R R R R R R R O
V V V V V V V V T V V V V V V V V
E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\eda\hxrjtd\cnt25.rpt
cnt25
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 2/ 8( 25%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 2/16( 12%) 3/ 8( 37%) 0/16( 0%) 0/36( 0%)
G: LC97 - LC112 7/16( 43%) 8/ 8(100%) 8/16( 50%) 5/36( 13%)
H: LC113 - LC128 16/16(100%) 7/ 8( 87%) 11/16( 68%) 11/36( 30%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 22/64 ( 34%)
Total logic cells used: 25/128 ( 19%)
Total shareable expanders used: 15/128 ( 11%)
Total Turbo logic cells used: 25/128 ( 19%)
Total shareable expanders not available (n/a): 4/128 ( 3%)
Average fan-in: 3.56
Total fan-in: 89
Total input pins required: 3
Total fast input logic cells required: 0
Total output pins required: 16
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 25
Total flipflops required: 5
Total product terms required: 88
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 14
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: d:\eda\hxrjtd\cnt25.rpt
cnt25
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 CLK
11 (5) (A) INPUT 0 0 0 0 0 0 5 EN25
12 (3) (A) INPUT 0 0 0 0 0 0 5 SB
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\eda\hxrjtd\cnt25.rpt
cnt25
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
73 115 H OUTPUT t 0 0 0 0 5 0 0 DOUT25B0
70 109 G OUTPUT t 7 1 1 0 5 0 0 DOUT25B1
80 126 H OUTPUT t 5 0 0 0 5 0 0 DOUT25B2
79 125 H OUTPUT t 5 1 1 0 5 0 0 DOUT25B3
77 123 H OUTPUT t 1 0 1 0 5 0 0 DOUT25B4
76 120 H OUTPUT t 0 0 0 0 5 0 0 DOUT25B5
64 99 G OUTPUT t 0 0 0 0 0 0 0 DOUT25B6
63 97 G OUTPUT t 0 0 0 0 0 0 0 DOUT25B7
81 128 H OUTPUT t 0 0 0 0 5 0 0 DOUT25M0
75 118 H OUTPUT t 0 0 0 0 4 0 0 DOUT25M1
65 101 G OUTPUT t 1 0 1 0 4 0 0 DOUT25M2
67 104 G OUTPUT t 0 0 0 0 4 0 0 DOUT25M3
69 107 G OUTPUT t 0 0 0 0 4 0 0 DOUT25M4
68 105 G OUTPUT t 0 0 0 0 4 0 0 DOUT25M5
55 85 F OUTPUT t 0 0 0 0 0 0 0 DOUT25M6
54 83 F OUTPUT t 0 0 0 0 0 0 0 DOUT25M7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda\hxrjtd\cnt25.rpt
cnt25
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 124 H SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node1
- 127 H SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node2
- 122 H SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node3
- 121 H SOFT t 0 0 0 0 5 0 1 |LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node4
- 113 H DFFE + t 0 0 0 2 1 12 1 CNTB4 (:20)
- 114 H DFFE + t 0 0 0 2 1 12 2 CNTB3 (:21)
- 119 H DFFE + t 0 0 0 2 1 12 3 CNTB2 (:22)
- 116 H DFFE + t 0 0 0 2 1 12 4 CNTB1 (:23)
(74) 117 H DFFE + t 0 0 0 2 1 7 5 CNTB0 (:24)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda\hxrjtd\cnt25.rpt
cnt25
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+--- LC85 DOUT25M6
| +- LC83 DOUT25M7
| |
| | Other LABs fed by signals
| | that feed LAB 'F'
LC | | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
83 -> - - | - - - - - - - - | <-- CLK
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda\hxrjtd\cnt25.rpt
cnt25
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+------------- LC109 DOUT25B1
| +----------- LC99 DOUT25B6
| | +--------- LC97 DOUT25B7
| | | +------- LC101 DOUT25M2
| | | | +----- LC104 DOUT25M3
| | | | | +--- LC107 DOUT25M4
| | | | | | +- LC105 DOUT25M5
| | | | | | |
| | | | | | | Other LABs fed by signals
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