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📄 xskz.rpt

📁 这是本人在Max plus2环境下用VHDL语言编的交通灯控制程序。做EDA课程设计的朋友可以下来参考参考。
💻 RPT
📖 第 1 页 / 共 5 页
字号:
   -     74    E      LCELL    s t        1      0   1    7    0    0    1  ~593~1~3
   -     60    D      LCELL    s t        0      0   0    0    2    0    1  ~593~1~4
 (52)    80    E      LCELL    s t        1      0   1    6    2    1    2  ~593~1
   -     78    E      LCELL    s t        1      0   1    7    1    0    1  ~608~1~2
 (49)    73    E      LCELL    s t        1      0   1    7    0    0    1  ~608~1~3
 (37)    56    D      LCELL    s t        0      0   0    0    2    0    1  ~608~1~4
   -     68    E      LCELL    s t        1      0   1    6    2    1    2  ~608~1
   -     81    F      LCELL    s t        1      0   1    7    1    0    1  ~623~1~2
 (54)    83    F      LCELL    s t        1      0   1    7    0    0    1  ~623~1~3
 (40)    51    D      LCELL    s t        0      0   0    0    2    0    1  ~623~1~4
   -     84    F      LCELL    s t        1      0   1    6    2    1    2  ~623~1
   -    102    G      LCELL    s t        1      0   1    7    1    0    1  ~638~1~2
 (68)   105    G      LCELL    s t        1      0   1    7    0    0    1  ~638~1~3
   -     63    D      LCELL    s t        0      0   0    0    2    0    1  ~638~1~4
 (71)   112    G      LCELL    s t        1      0   1    6    2    1    2  ~638~1
   -    114    H      LCELL    s t        1      0   1    7    1    0    1  ~653~1~2
   -    113    H      LCELL    s t        1      0   1    7    0    0    1  ~653~1~3
 (35)    59    D      LCELL    s t        0      0   0    0    2    0    1  ~653~1~4
   -    124    H      LCELL    s t        1      0   1    6    2    1    2  ~653~1
 (77)   123    H      LCELL    s t        1      0   1    7    1    0    1  ~668~1~2
   -    122    H      LCELL    s t        1      0   1    7    0    0    1  ~668~1~3
   -     58    D      LCELL    s t        0      0   0    0    2    0    1  ~668~1~4
   -    121    H      LCELL    s t        1      0   1    6    2    1    2  ~668~1
 (65)   101    G      LCELL    s t        1      0   1    7    1    0    1  ~683~1~2
   -    103    G      LCELL    s t        1      0   1    7    0    0    1  ~683~1~3
 (41)    49    D      LCELL    s t        0      0   0    0    2    0    1  ~683~1~4
   -    100    G      LCELL    s t        1      0   1    6    2    1    2  ~683~1
   -     90    F      LCELL    s t        1      0   1    7    1    0    1  ~698~1~2
 (55)    85    F      LCELL    s t        1      0   1    7    0    0    1  ~698~1~3
   -     52    D      LCELL    s t        0      0   0    0    2    0    1  ~698~1~4
   -     87    F      LCELL    s t        1      0   1    6    2    1    2  ~698~1
   -     79    E      LCELL    s t        1      0   1    7    1    0    1  ~713~1~2
   -     66    E      LCELL    s t        1      0   1    7    0    0    1  ~713~1~3
 (39)    53    D      LCELL    s t        0      0   0    0    2    0    1  ~713~1~4
 (46)    69    E      LCELL    s t        1      0   1    6    2    1    2  ~713~1
   -     70    E      LCELL    s t        1      0   1    7    1    0    1  ~728~1~2
   -     71    E      LCELL    s t        1      0   1    7    0    0    1  ~728~1~3
   -     54    D      LCELL    s t        0      0   0    0    2    0    1  ~728~1~4
 (51)    77    E      LCELL    s t        1      0   1    6    2    1    2  ~728~1
   -     89    F      LCELL    s t        1      0   1    7    1    0    1  ~743~1~2
   -     82    F      LCELL    s t        1      0   1    7    0    0    1  ~743~1~3
 (31)    35    C      LCELL    s t        0      0   0    0    2    0    1  ~743~1~4
 (56)    86    F      LCELL    s t        1      0   1    6    2    1    2  ~743~1
   -     98    G      LCELL    s t        1      0   1    7    1    0    1  ~758~1~2
 (64)    99    G      LCELL    s t        1      0   1    7    0    0    1  ~758~1~3
 (28)    40    C      LCELL    s t        0      0   0    0    2    0    1  ~758~1~4
   -    106    G      LCELL    s t        1      0   1    6    2    1    2  ~758~1
 (80)   126    H      LCELL    s t        1      0   1    7    1    0    1  ~773~1~2
   -    127    H      LCELL    s t        1      0   1    7    0    0    1  ~773~1~3
   -     41    C      LCELL    s t        0      0   0    0    2    0    1  ~773~1~4
 (81)   128    H      LCELL    s t        1      0   1    6    2    1    2  ~773~1


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                            d:\eda\hxrjtd\xskz.rpt
xskz

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

               Logic cells placed in LAB 'C'
        +----- LC35 ~743~1~4
        | +--- LC40 ~758~1~4
        | | +- LC41 ~773~1~4
        | | | 
        | | |   Other LABs fed by signals
        | | |   that feed LAB 'C'
LC      | | | | A B C D E F G H |     Logic cells that feed LAB 'C':

Pin
84   -> - - - | - - - - - * - - | <-- AIN25B2
LC89 -> * - - | - - * - - - - - | <-- ~743~1~2
LC82 -> * - - | - - * - - - - - | <-- ~743~1~3
LC98 -> - * - | - - * - - - - - | <-- ~758~1~2
LC99 -> - * - | - - * - - - - - | <-- ~758~1~3
LC126-> - - * | - - * - - - - - | <-- ~773~1~2
LC127-> - - * | - - * - - - - - | <-- ~773~1~3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            d:\eda\hxrjtd\xskz.rpt
xskz

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                   Logic cells placed in LAB 'D'
        +------------------------- LC50 ~548~1~4
        | +----------------------- LC55 ~563~1~4
        | | +--------------------- LC62 ~578~1~4
        | | | +------------------- LC60 ~593~1~4
        | | | | +----------------- LC56 ~608~1~4
        | | | | | +--------------- LC51 ~623~1~4
        | | | | | | +------------- LC63 ~638~1~4
        | | | | | | | +----------- LC59 ~653~1~4
        | | | | | | | | +--------- LC58 ~668~1~4
        | | | | | | | | | +------- LC49 ~683~1~4
        | | | | | | | | | | +----- LC52 ~698~1~4
        | | | | | | | | | | | +--- LC53 ~713~1~4
        | | | | | | | | | | | | +- LC54 ~728~1~4
        | | | | | | | | | | | | | 
        | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'D':

Pin
84   -> - - - - - - - - - - - - - | - - - - - * - - | <-- AIN25B2
LC125-> * - - - - - - - - - - - - | - - - * - - - - | <-- ~548~1~2
LC119-> * - - - - - - - - - - - - | - - - * - - - - | <-- ~548~1~3
LC108-> - * - - - - - - - - - - - | - - - * - - - - | <-- ~563~1~2
LC110-> - * - - - - - - - - - - - | - - - * - - - - | <-- ~563~1~3
LC96 -> - - * - - - - - - - - - - | - - - * - - - - | <-- ~578~1~2
LC92 -> - - * - - - - - - - - - - | - - - * - - - - | <-- ~578~1~3
LC76 -> - - - * - - - - - - - - - | - - - * - - - - | <-- ~593~1~2
LC74 -> - - - * - - - - - - - - - | - - - * - - - - | <-- ~593~1~3
LC78 -> - - - - * - - - - - - - - | - - - * - - - - | <-- ~608~1~2
LC73 -> - - - - * - - - - - - - - | - - - * - - - - | <-- ~608~1~3
LC81 -> - - - - - * - - - - - - - | - - - * - - - - | <-- ~623~1~2
LC83 -> - - - - - * - - - - - - - | - - - * - - - - | <-- ~623~1~3
LC102-> - - - - - - * - - - - - - | - - - * - - - - | <-- ~638~1~2
LC105-> - - - - - - * - - - - - - | - - - * - - - - | <-- ~638~1~3
LC114-> - - - - - - - * - - - - - | - - - * - - - - | <-- ~653~1~2
LC113-> - - - - - - - * - - - - - | - - - * - - - - | <-- ~653~1~3
LC123-> - - - - - - - - * - - - - | - - - * - - - - | <-- ~668~1~2
LC122-> - - - - - - - - * - - - - | - - - * - - - - | <-- ~668~1~3
LC101-> - - - - - - - - - * - - - | - - - * - - - - | <-- ~683~1~2
LC103-> - - - - - - - - - * - - - | - - - * - - - - | <-- ~683~1~3
LC90 -> - - - - - - - - - - * - - | - - - * - - - - | <-- ~698~1~2
LC85 -> - - - - - - - - - - * - - | - - - * - - - - | <-- ~698~1~3
LC79 -> - - - - - - - - - - - * - | - - - * - - - - | <-- ~713~1~2
LC66 -> - - - - - - - - - - - * - | - - - * - - - - | <-- ~713~1~3
LC70 -> - - - - - - - - - - - - * | - - - * - - - - | <-- ~728~1~2
LC71 -> - - - - - - - - - - - - * | - - - * - - - - | <-- ~728~1~3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            d:\eda\hxrjtd\xskz.rpt
xskz

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                                         Logic cells placed in LAB 'E'
        +------------------------------- LC75 DOUTB3
        | +----------------------------- LC72 DOUTB4
        | | +--------------------------- LC65 DOUTM3
        | | | +------------------------- LC67 DOUTM4
        | | | | +----------------------- LC76 ~593~1~2
        | | | | | +--------------------- LC74 ~593~1~3
        | | | | | | +------------------- LC80 ~593~1
        | | | | | | | +----------------- LC78 ~608~1~2
        | | | | | | | | +--------------- LC73 ~608~1~3
        | | | | | | | | | +------------- LC68 ~608~1
        | | | | | | | | | | +----------- LC79 ~713~1~2
        | | | | | | | | | | | +--------- LC66 ~713~1~3
        | | | | | | | | | | | | +------- LC69 ~713~1
        | | | | | | | | | | | | | +----- LC70 ~728~1~2
        | | | | | | | | | | | | | | +--- LC71 ~728~1~3
        | | | | | | | | | | | | | | | +- LC77 ~728~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':
LC80 -> - - - * * - * - - - - - - - - - | - - - - * - - - | <-- ~593~1
LC68 -> - - * - - - - * - * - - - - - - | - - - - * - - - | <-- ~608~1
LC69 -> - * - - - - - - - - * - * - - - | - - - - * - - - | <-- ~713~1
LC77 -> * - - - - - - - - - - - - * - * | - - - - * - - - | <-- ~728~1

Pin
28   -> * - - - - - - - - - - - - * * * | - - - - * - - - | <-- AIN15B3
68   -> - * - - - - - - - - * * * - - - | - - - - * - - - | <-- AIN15B4
35   -> - - * - - - - * * * - - - - - - | - - - - * - - - | <-- AIN15M3
46   -> - - - * * * * - - - - - - - - - | - - - - * - - - | <-- AIN15M4
84   -> - - - - - - - - - - - - - - - - | - - - - - * - - | <-- AIN25B2
81   -> * - - - - - - - - - - - - * * - | - - - - * - - - | <-- AIN25B3
79   -> - * - - - - - - - - * * - - - - | - - - - * - - - | <-- AIN25B4
6    -> - - * - - - - * * - - - - - - - | - - - - * - - - | <-- AIN25M3
5    -> - - - * * * - - - - - - - - - - | - - - - * - - - | <-- AIN25M4
15   -> * - * - - - - * * * - - - * * * | - - - - * - - - | <-- AIN53
31   -> - * - * * * * - - - * * * - - - | - - - - * - - - | <-- AIN54
12   -> * * * * * * * * * * * * * * * * | - - - - * * * * | <-- EN5B
11   -> * * * * * * * * * * * * * * * * | - - - - * * * * | <-- EN5M
10   -> * * * * * * * * * * * * * * * * | - - - - * * * * | <-- EN15
9    -> * * * * * * * * * * * * * * * * | - - - - * * * * | <-- EN25
LC60 -> - - - - - - * - - - - - - - - - | - - - - * - - - | <-- ~593~1~4
LC56 -> - - - - - - - - - * - - - - - - | - - - - * - - - | <-- ~608~1~4
LC53 -> - - - - - - - - - - - - * - - - | - - - - * - - - | <-- ~713~1~4
LC54 -> - - - - - - - - - - - - - - - * | - - - - * - - - | <-- ~728~1~4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            d:\eda\hxrjtd\xskz.rpt
xskz

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                                         Logic cells placed in LAB 'F'
        +------------------------------- LC94 DOUTB2
        | +----------------------------- LC88 DOUTB5
        | | +--------------------------- LC93 DOUTM2
        | | | +------------------------- LC91 DOUTM5
        | | | | +----------------------- LC96 ~578~1~2
        | | | | | +--------------------- LC92 ~578~1~3
        | | | | | | +------------------- LC95 ~578~1
        | | | | | | | +----------------- LC81 ~623~1~2
        | | | | | | | | +--------------- LC83 ~623~1~3
        | | | | | | | | | +------------- LC84 ~623~1
        | | | | | | | | | | +----------- LC90 ~698~1~2
        | | | | | | | | | | | +--------- LC85 ~698~1~3
        | | | | | | | | | | | | +------- LC87 ~698~1
        | | | | | | | | | | | | | +----- LC89 ~743~1~2
        | | | | | | | | | | | | | | +--- LC82 ~743~1~3
        | | | | | | | | | | | | | | | +- LC86 ~743~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'F':
LC95 -> - - - * * - * - - - - - - - - - | - - - - - * - - | <-- ~578~1
LC84 -> - - * - - - - * - * - - - - - - | - - - - - * - - | <-- ~623~1
LC87 -> - * - - - - - - - - * - * - - - | - - - - - * - - | <-- ~698~1
LC86 -> * - - - - - - - - - - - - * - * | - - - - - * - - | <-- ~743~1

Pin
30   -> * - - - - - - - - - - - - * * * | - - - - - * - - | <-- AIN15B2
36   -> - * - - - - - - - - * * * - - - | - - - - - * - - | <-- AIN15B5
52   -> - - * - - - - * * * - - - - - - | - - - - - * - - | <-- AIN15M2
64   -> - - - * * * * - - - - - - - - - | - - - - - * - - | <-- AIN15M5
84   -> * - - - - - - - - - - - - * * - | - - - - - * - - | <-- AIN25B2
55   -> - * - - - - - - - - * * - - - - | - - - - - * - - | <-- AIN25B5
8    -> - - * - - - - * * - - - - - - - | - - - - - * - - | <-- AIN25M2
4    -> - - - * * * - - - - - - - - - - | - - - - - * - - | <-- AIN25M5
16   -> * - * - - - - * * * - - - * * * | - - - - - * - - | <-- AIN52
29   -> - * - * * * * - - - * * * - - - | - - - - - * - - | <-- AIN55
12   -> * * * * * * * * * * * * * * * * | - - - - * * * * | <-- EN5B
11   -> * * * * * * * * * * * * * * * * | - - - - * * * * | <-- EN5M
10   -> * * * * * * * * * * * * * * * * | - - - - * * * * | <-- EN15
9    -> * * * * * * * * * * * * * * * * | - - - - * * * * | <-- EN25
LC62 -> - - - - - - * - - - - - - - - - | - - - - - * - - | <-- ~578~1~4
LC51 -> - - - - - - - - - * - - - - - - | - - - - - * - - | <-- ~623~1~4
LC52 -> - - - - - - - - - - - - * - - - | - - - - - * - - | <-- ~698~1~4
LC35 -> - - - - - - - - - - - - - - - * | - - - - - * - - | <-- ~743~1~4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            d:\eda\hxrjtd\xskz.rpt
xskz

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                                         Logic cells placed in LAB 'G'
        +------------------------------- LC97 DOUTB1
        | +----------------------------- LC109 DOUTB6
        | | +--------------------------- LC107 DOUTM1
        | | | +------------------------- LC104 DOUTM6
        | | | | +----------------------- LC108 ~563~1~2
        | | | | | +--------------------- LC110 ~563~1~3
        | | | | | | +------------------- LC111 ~563~1
        | | | | | | | +----------------- LC102 ~638~1~2
        | | | | | | | | +--------------- LC105 ~638~1~3
        | | | | | | | | | +------------- LC112 ~638~1
        | | | | | | | | | | +----------- LC101 ~683~1~2
        | | | | | | | | | | | +--------- LC103 ~683~1~3
        | | | | | | | | | | | | +------- LC100 ~683~1

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