📄 xskz.rpt
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Project Information d:\eda\hxrjtd\xskz.rpt
MAX+plus II Compiler Report File
Version 10.12 09/21/2001
Compiled: 06/08/2006 20:56:49
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
XSKZ
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
xskz EPM7128SLC84-15 44 16 0 80 0 62 %
User Pins: 44 16 0
Device-Specific Information: d:\eda\hxrjtd\xskz.rpt
xskz
***** Logic for device 'xskz' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
Device-Specific Information: d:\eda\hxrjtd\xskz.rpt
xskz
** ERROR SUMMARY **
Info: Chip 'xskz' in device 'EPM7128SLC84-15' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
A A A A A A A A A
I I I I V I I I I I D D
N N N N C N N N N V N O O
E E E 2 2 2 2 C 2 2 2 2 C 2 U U
N N N 5 G 5 5 5 I G G 5 G G 5 5 5 C 5 T T
5 1 2 M N M M M N N N B N N B B B I B M B
M 5 5 2 D 3 4 5 T D D 2 D D 3 1 4 O 0 7 7
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
EN5B | 12 74 | DOUTM0
VCCIO | 13 73 | DOUTB0
#TDI | 14 72 | GND
AIN53 | 15 71 | #TDO
AIN52 | 16 70 | DOUTB6
AIN51 | 17 69 | DOUTM1
AIN50 | 18 68 | AIN15B4
GND | 19 67 | DOUTM6
AIN25M7 | 20 66 | VCCIO
AIN25M6 | 21 65 | AIN25B7
AIN15B1 | 22 EPM7128SLC84-15 64 | AIN15M5
#TMS | 23 63 | DOUTB1
AIN15B7 | 24 62 | #TCK
AIN15M0 | 25 61 | DOUTB2
VCCIO | 26 60 | DOUTM2
AIN56 | 27 59 | GND
AIN15B3 | 28 58 | DOUTM5
AIN55 | 29 57 | DOUTB5
AIN15B2 | 30 56 | RESERVED
AIN54 | 31 55 | AIN25B5
GND | 32 54 | AIN15M1
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
A A A A A V A A A G V D D A G D A D A A V
I I I I I C I I I N C O O I N O I O I I C
N N N N N C N N N D C U U N D U N U N N C
2 2 1 1 1 I 1 1 5 I T T 1 T 1 T 2 1 I
5 5 5 5 5 O 5 5 7 N M M 5 B 5 B 5 5 O
M M M B B B M T 3 4 M 4 M 3 B M
0 1 3 5 0 6 7 4 6 6 2
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\eda\hxrjtd\xskz.rpt
xskz
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 3/16( 18%) 8/ 8(100%) 0/16( 0%) 6/36( 16%)
D: LC49 - LC64 13/16( 81%) 8/ 8(100%) 0/16( 0%) 26/36( 72%)
E: LC65 - LC80 16/16(100%) 8/ 8(100%) 16/16(100%) 22/36( 61%)
F: LC81 - LC96 16/16(100%) 7/ 8( 87%) 16/16(100%) 22/36( 61%)
G: LC97 - LC112 16/16(100%) 8/ 8(100%) 16/16(100%) 22/36( 61%)
H: LC113 - LC128 16/16(100%) 8/ 8(100%) 16/16(100%) 22/36( 61%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 63/64 ( 98%)
Total logic cells used: 80/128 ( 62%)
Total shareable expanders used: 0/128 ( 0%)
Total Turbo logic cells used: 80/128 ( 62%)
Total shareable expanders not available (n/a): 64/128 ( 50%)
Average fan-in: 6.60
Total fan-in: 528
Total input pins required: 44
Total fast input logic cells required: 0
Total output pins required: 16
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 80
Total flipflops required: 0
Total product terms required: 352
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 64/ 128 ( 50%)
Device-Specific Information: d:\eda\hxrjtd\xskz.rpt
xskz
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
37 (56) (D) INPUT 0 0 0 0 0 1 3 AIN15B0
22 (17) (B) INPUT 0 0 0 0 0 1 3 AIN15B1
30 (37) (C) INPUT 0 0 0 0 0 1 3 AIN15B2
28 (40) (C) INPUT 0 0 0 0 0 1 3 AIN15B3
68 (105) (G) INPUT 0 0 0 0 0 1 3 AIN15B4
36 (57) (D) INPUT 0 0 0 0 0 1 3 AIN15B5
39 (53) (D) INPUT 0 0 0 0 0 1 3 AIN15B6
24 (46) (C) INPUT 0 0 0 0 0 1 3 AIN15B7
25 (45) (C) INPUT 0 0 0 0 0 1 3 AIN15M0
54 (83) (F) INPUT 0 0 0 0 0 1 3 AIN15M1
52 (80) (E) INPUT 0 0 0 0 0 1 3 AIN15M2
35 (59) (D) INPUT 0 0 0 0 0 1 3 AIN15M3
46 (69) (E) INPUT 0 0 0 0 0 1 3 AIN15M4
64 (99) (G) INPUT 0 0 0 0 0 1 3 AIN15M5
49 (73) (E) INPUT 0 0 0 0 0 1 3 AIN15M6
40 (51) (D) INPUT 0 0 0 0 0 1 3 AIN15M7
77 (123) (H) INPUT 0 0 0 0 0 1 2 AIN25B0
80 (126) (H) INPUT 0 0 0 0 0 1 2 AIN25B1
84 - - INPUT 0 0 0 0 0 1 2 AIN25B2
81 (128) (H) INPUT 0 0 0 0 0 1 2 AIN25B3
79 (125) (H) INPUT 0 0 0 0 0 1 2 AIN25B4
55 (85) (F) INPUT 0 0 0 0 0 1 2 AIN25B5
51 (77) (E) INPUT 0 0 0 0 0 1 2 AIN25B6
65 (101) (G) INPUT 0 0 0 0 0 1 2 AIN25B7
33 (64) (D) INPUT 0 0 0 0 0 1 2 AIN25M0
34 (61) (D) INPUT 0 0 0 0 0 1 2 AIN25M1
8 (11) (A) INPUT 0 0 0 0 0 1 2 AIN25M2
6 (13) (A) INPUT 0 0 0 0 0 1 2 AIN25M3
5 (14) (A) INPUT 0 0 0 0 0 1 2 AIN25M4
4 (16) (A) INPUT 0 0 0 0 0 1 2 AIN25M5
21 (19) (B) INPUT 0 0 0 0 0 1 2 AIN25M6
20 (21) (B) INPUT 0 0 0 0 0 1 2 AIN25M7
18 (24) (B) INPUT 0 0 0 0 0 2 6 AIN50
17 (25) (B) INPUT 0 0 0 0 0 2 6 AIN51
16 (27) (B) INPUT 0 0 0 0 0 2 6 AIN52
15 (29) (B) INPUT 0 0 0 0 0 2 6 AIN53
31 (35) (C) INPUT 0 0 0 0 0 2 6 AIN54
29 (38) (C) INPUT 0 0 0 0 0 2 6 AIN55
27 (43) (C) INPUT 0 0 0 0 0 2 6 AIN56
41 (49) (D) INPUT 0 0 0 0 0 2 6 AIN57
12 (3) (A) INPUT 0 0 0 0 0 16 48 EN5B
11 (5) (A) INPUT 0 0 0 0 0 16 48 EN5M
10 (6) (A) INPUT 0 0 0 0 0 16 48 EN15
9 (8) (A) INPUT 0 0 0 0 0 16 48 EN25
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda\hxrjtd\xskz.rpt
xskz
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
73 115 H OUTPUT t 1 0 1 7 1 0 0 DOUTB0
63 97 G OUTPUT t 1 0 1 7 1 0 0 DOUTB1
61 94 F OUTPUT t 1 0 1 7 1 0 0 DOUTB2
50 75 E OUTPUT t 1 0 1 7 1 0 0 DOUTB3
48 72 E OUTPUT t 1 0 1 7 1 0 0 DOUTB4
57 88 F OUTPUT t 1 0 1 7 1 0 0 DOUTB5
70 109 G OUTPUT t 1 0 1 7 1 0 0 DOUTB6
75 118 H OUTPUT t 1 0 1 7 1 0 0 DOUTB7
74 117 H OUTPUT t 1 0 1 7 1 0 0 DOUTM0
69 107 G OUTPUT t 1 0 1 7 1 0 0 DOUTM1
60 93 F OUTPUT t 1 0 1 7 1 0 0 DOUTM2
44 65 E OUTPUT t 1 0 1 7 1 0 0 DOUTM3
45 67 E OUTPUT t 1 0 1 7 1 0 0 DOUTM4
58 91 F OUTPUT t 1 0 1 7 1 0 0 DOUTM5
67 104 G OUTPUT t 1 0 1 7 1 0 0 DOUTM6
76 120 H OUTPUT t 1 0 1 7 1 0 0 DOUTM7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda\hxrjtd\xskz.rpt
xskz
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(79) 125 H LCELL s t 1 0 1 7 1 0 1 ~548~1~2
- 119 H LCELL s t 1 0 1 7 0 0 1 ~548~1~3
- 50 D LCELL s t 0 0 0 0 2 0 1 ~548~1~4
- 116 H LCELL s t 1 0 1 6 2 1 2 ~548~1
- 108 G LCELL s t 1 0 1 7 1 0 1 ~563~1~2
- 110 G LCELL s t 1 0 1 7 0 0 1 ~563~1~3
- 55 D LCELL s t 0 0 0 0 2 0 1 ~563~1~4
- 111 G LCELL s t 1 0 1 6 2 1 2 ~563~1
(62) 96 F LCELL s t 1 0 1 7 1 0 1 ~578~1~2
- 92 F LCELL s t 1 0 1 7 0 0 1 ~578~1~3
- 62 D LCELL s t 0 0 0 0 2 0 1 ~578~1~4
- 95 F LCELL s t 1 0 1 6 2 1 2 ~578~1
- 76 E LCELL s t 1 0 1 7 1 0 1 ~593~1~2
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