📄 jtdkz.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY JTDKZ IS
PORT(CLK,SM,SB: IN STD_LOGIC;
MR,MY,MG,BR,BY,BG: OUT STD_LOGIC);
END ENTITY JTDKZ;
ARCHITECTURE one OF JTDKZ IS
TYPE STATE_TYPE IS (A,B,C,D);
SIGNAL STATE: STATE_TYPE;
BEGIN
CNT: PROCESS(CLK) IS
VARIABLE S:INTEGER RANGE 0 TO 25;
VARIABLE CLR,EN :BIT;
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
IF CLR='0' THEN
S:=0;
ELSIF EN='0' THEN
S:=S;
ELSE
S:=S+1;
END IF;
CASE STATE IS
WHEN A=>MR<='0';MY<='0';MG<='1';
BR<='1';BY<='0';BG<='0';
IF(SB AND SM)='1' THEN
IF S=25 THEN
STATE<=B;CLR:='0';EN:='0';
ELSE
STATE<=A;CLR:='1';EN:='1';
END IF;
ELSIF (SB AND (NOT SM))='1' THEN
STATE<=B;CLR:='0';EN:='0';
ELSE
STATE<=A; CLR:='1';EN:='1';
END IF;
WHEN B=>MR<='0';MY<='1';MG<='0';
BR<='1';BY<='0';BG<='0';
IF S=5 THEN
STATE<=C;CLR:='0';EN:='0';
ELSE
STATE<=B;CLR:='1';EN:='1';
END IF;
WHEN C=>MR<='1';MY<='0';MG<='0';
BR<='0';BY<='0';BG<='1';
IF (SM AND SB)='1' THEN
IF S=15 THEN
STATE<=D; CLR:='0';EN:='0';
ELSE
STATE<=C;CLR:='1';EN:='1';
END IF;
ELSIF SB='0'THEN
STATE<=D;CLR:='0';EN:='0';
ELSE
STATE<=C;CLR:='1';EN:='1';
END IF;
WHEN D=>MR<='1';MY<='0';MG<='0';
BR<='0';BY<='1';BG<='0';
IF S=5 THEN
STATE<=A;CLR:='0';EN:='0';
ELSE
STATE<=D;CLR:='1';EN:='1';
END IF;
END CASE;
END IF;
END PROCESS CNT;
END ARCHITECTURE one;
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