📄 jtdkz.rpt
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-- Equation name is 'MR', type is output
MR = DFFE(!STATE1 $ VCC, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'MY' = ':6'
-- Equation name is 'MY', type is output
MY = DFFE( _EQ008 $ STATE0, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = STATE0 & STATE1;
-- Node name is ':17' = 'STATE0'
-- Equation name is 'STATE0', location is LC114, type is buried.
STATE0 = DFFE( _EQ009 $ _EQ010, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = CLR & EN & !_LC098 & !_LC104 & _LC113 & !_LC121 & !_LC123 &
STATE0 & !S0 & !S3 & _X007 & _X009 & _X010 & _X011 & _X012 &
_X013 & _X014 & _X015 & _X016 & _X017 & _X018 & _X019 &
_X020
# CLR & !EN & !_LC104 & !_LC123 & STATE0 & S0 & !S1 & S2 & !S3 &
!S4 & _X009 & _X010 & _X011 & _X012 & _X013 & _X014 &
_X015 & _X016 & _X017 & _X018 & _X019 & _X020;
_X007 = EXP( S0 & S1 & S2);
_X009 = EXP(!_LC121 & SM & !STATE0 & !STATE1 & !S0);
_X010 = EXP(!_LC113 & SB & !STATE0 & STATE1 & !S3);
_X011 = EXP(!_LC113 & SB & !STATE0 & STATE1 & !S0);
_X012 = EXP(!_LC098 & SB & !STATE0 & STATE1 & !S3);
_X013 = EXP(!_LC098 & SB & !STATE0 & STATE1 & !S0);
_X014 = EXP( _LC098 & SM & !STATE0 & !STATE1 & !S0);
_X015 = EXP( _LC113 & SM & !STATE0 & !STATE1 & !S0);
_X016 = EXP(!EN & SM & !STATE0 & !STATE1 & S2);
_X017 = EXP(!EN & SM & !STATE0 & !STATE1 & S1);
_X018 = EXP(!SB & !STATE0 & !STATE1);
_X019 = EXP( SB & !SM & !STATE0 & STATE1);
_X020 = EXP(!CLR & SB & SM & !STATE0);
_EQ010 = !_LC104 & !_LC123 & _X009 & _X010 & _X011 & _X012 & _X013 &
_X014 & _X015 & _X016 & _X017 & _X018 & _X019 & _X020;
_X009 = EXP(!_LC121 & SM & !STATE0 & !STATE1 & !S0);
_X010 = EXP(!_LC113 & SB & !STATE0 & STATE1 & !S3);
_X011 = EXP(!_LC113 & SB & !STATE0 & STATE1 & !S0);
_X012 = EXP(!_LC098 & SB & !STATE0 & STATE1 & !S3);
_X013 = EXP(!_LC098 & SB & !STATE0 & STATE1 & !S0);
_X014 = EXP( _LC098 & SM & !STATE0 & !STATE1 & !S0);
_X015 = EXP( _LC113 & SM & !STATE0 & !STATE1 & !S0);
_X016 = EXP(!EN & SM & !STATE0 & !STATE1 & S2);
_X017 = EXP(!EN & SM & !STATE0 & !STATE1 & S1);
_X018 = EXP(!SB & !STATE0 & !STATE1);
_X019 = EXP( SB & !SM & !STATE0 & STATE1);
_X020 = EXP(!CLR & SB & SM & !STATE0);
-- Node name is ':16' = 'STATE1'
-- Equation name is 'STATE1', location is LC122, type is buried.
STATE1 = TFFE( _EQ011, GLOBAL( CLK), VCC, VCC, VCC);
_EQ011 = CLR & EN & !_LC098 & _LC113 & !_LC121 & !_LC126 & STATE0 & !S0
# CLR & !EN & STATE0 & S0 & !S1 & S2 & !S3 & !S4;
-- Node name is ':22' = 'S0'
-- Equation name is 'S0', location is LC119, type is buried.
S0 = DFFE( _EQ012 $ CLR, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = CLR & EN & S0
# CLR & !EN & !S0;
-- Node name is ':21' = 'S1'
-- Equation name is 'S1', location is LC118, type is buried.
S1 = DFFE( _EQ013 $ CLR, GLOBAL( CLK), VCC, VCC, VCC);
_EQ013 = CLR & EN & !_LC098
# CLR & !EN & !S1;
-- Node name is ':20' = 'S2'
-- Equation name is 'S2', location is LC117, type is buried.
S2 = DFFE( _EQ014 $ CLR, GLOBAL( CLK), VCC, VCC, VCC);
_EQ014 = CLR & EN & !_LC113
# CLR & !EN & !S2;
-- Node name is ':19' = 'S3'
-- Equation name is 'S3', location is LC116, type is buried.
S3 = DFFE( _EQ015 $ CLR, GLOBAL( CLK), VCC, VCC, VCC);
_EQ015 = CLR & EN & !_LC126
# CLR & !EN & !S3;
-- Node name is ':18' = 'S4'
-- Equation name is 'S4', location is LC115, type is buried.
S4 = DFFE( _EQ016 $ CLR, GLOBAL( CLK), VCC, VCC, VCC);
_EQ016 = CLR & EN & !_LC121
# CLR & !EN & !S4;
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC124', type is buried
_LC124 = LCELL( _EQ017 $ GND);
_EQ017 = S0 & S1 & S2;
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC098', type is buried
_LC098 = LCELL( S1 $ S0);
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC113', type is buried
_LC113 = LCELL( S2 $ _EQ018);
_EQ018 = S0 & S1;
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC126', type is buried
_LC126 = LCELL( S3 $ _EQ019);
_EQ019 = S0 & S1 & S2;
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC121', type is buried
_LC121 = LCELL( S4 $ _EQ020);
_EQ020 = S0 & S1 & S2 & S3;
-- Node name is '~748~1'
-- Equation name is '~748~1', location is LC123, type is buried.
-- synthesized logic cell
_LC123 = LCELL( _EQ021 $ GND);
_EQ021 = EN & SB & SM & !STATE0 & S0
# SB & !STATE0 & STATE1 & S0 & !S2
# SB & !STATE0 & STATE1 & S0 & !S1
# _LC121 & SB & !STATE0 & STATE1 & !S0
# !EN & SB & !STATE0 & STATE1 & S4;
-- Node name is '~748~2'
-- Equation name is '~748~2', location is LC104, type is buried.
-- synthesized logic cell
_LC104 = LCELL( _EQ022 $ GND);
_EQ022 = !EN & SB & SM & !STATE0 & !S3
# !_LC124 & SB & SM & !STATE0 & !S3
# !EN & SB & SM & !STATE0 & !S0
# SM & !STATE0 & !STATE1 & S0 & !S4
# SM & !STATE0 & !STATE1 & S0 & !S3;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X007 occurs in LABs G, H
Project Information d:\eda\hxrjtd\jtdkz.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,777K
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