📄 jtdkz.rpt
字号:
65 101 G FF + t 0 0 0 0 1 0 0 MR
68 105 G FF + t 0 0 0 0 2 0 0 MY
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda\hxrjtd\jtdkz.rpt
jtdkz
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 124 H SOFT t 0 0 0 0 3 0 3 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gcp2
- 98 G SOFT t 0 0 0 0 2 0 4 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node1
- 113 H SOFT t 0 0 0 0 3 0 4 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node2
(80) 126 H SOFT t 0 0 0 0 4 0 2 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3
- 121 H SOFT t 0 0 0 0 5 0 6 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node4
- 122 H TFFE + t 0 0 0 0 12 6 5 STATE1 (:16)
- 114 H DFFE + t 13 1 0 2 14 4 6 STATE0 (:17)
(73) 115 H DFFE + t 0 0 0 0 4 0 8 S4 (:18)
- 116 H DFFE + t 0 0 0 0 4 0 8 S3 (:19)
(74) 117 H DFFE + t 0 0 0 0 4 0 10 S2 (:20)
(75) 118 H DFFE + t 0 0 0 0 4 0 11 S1 (:21)
- 119 H DFFE + t 0 0 0 0 3 0 12 S0 (:22)
- 100 G DFFE + t 7 6 0 2 11 0 9 CLR (:23)
(63) 97 G DFFE + t 7 6 0 2 13 0 11 EN (:24)
(77) 123 H SOFT s t 1 0 1 2 8 0 1 ~748~1
(67) 104 G SOFT s t 1 0 1 2 7 0 1 ~748~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda\hxrjtd\jtdkz.rpt
jtdkz
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+------------- LC99 BR
| +----------- LC98 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node1
| | +--------- LC101 MR
| | | +------- LC105 MY
| | | | +----- LC100 CLR
| | | | | +--- LC97 EN
| | | | | | +- LC104 ~748~2
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'G'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC98 -> - - - - - * - | - - - - - - * * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node1
LC100-> - - - - * * - | - - - - - - * * | <-- CLR
LC97 -> - - - - * * * | - - - - - - * * | <-- EN
Pin
83 -> - - - - - - - | - - - - - - - - | <-- CLK
12 -> - - - - * * * | - - - - - - * * | <-- SB
11 -> - - - - * * * | - - - - - - * * | <-- SM
LC124-> - - - - * * * | - - - - - - * - | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gcp2
LC113-> - - - - - * - | - - - - - - * * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node2
LC121-> - - - - * * - | - - - - - - * * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node4
LC122-> * - * * * * * | - - - - - - * * | <-- STATE1
LC114-> - - - * * * * | - - - - - - * * | <-- STATE0
LC115-> - - - - * * * | - - - - - - * * | <-- S4
LC116-> - - - - * * * | - - - - - - * * | <-- S3
LC117-> - - - - * * - | - - - - - - * * | <-- S2
LC118-> - * - - * * - | - - - - - - * * | <-- S1
LC119-> - * - - * * * | - - - - - - * * | <-- S0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda\hxrjtd\jtdkz.rpt
jtdkz
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+----------------------------- LC120 BG
| +--------------------------- LC125 BY
| | +------------------------- LC124 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gcp2
| | | +----------------------- LC113 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node2
| | | | +--------------------- LC126 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3
| | | | | +------------------- LC121 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node4
| | | | | | +----------------- LC128 MG
| | | | | | | +--------------- LC122 STATE1
| | | | | | | | +------------- LC114 STATE0
| | | | | | | | | +----------- LC115 S4
| | | | | | | | | | +--------- LC116 S3
| | | | | | | | | | | +------- LC117 S2
| | | | | | | | | | | | +----- LC118 S1
| | | | | | | | | | | | | +--- LC119 S0
| | | | | | | | | | | | | | +- LC123 ~748~1
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC113-> - - - - - - - * * - - * - - - | - - - - - - * * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node2
LC126-> - - - - - - - * - - * - - - - | - - - - - - - * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3
LC121-> - - - - - - - * * * - - - - * | - - - - - - * * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node4
LC122-> * * - - - - * * * - - - - - * | - - - - - - * * | <-- STATE1
LC114-> * * - - - - * * * - - - - - * | - - - - - - * * | <-- STATE0
LC115-> - - - - - * - * * * - - - - * | - - - - - - * * | <-- S4
LC116-> - - - - * * - * * - * - - - - | - - - - - - * * | <-- S3
LC117-> - - * * * * - * * - - * - - * | - - - - - - * * | <-- S2
LC118-> - - * * * * - * * - - - * - * | - - - - - - * * | <-- S1
LC119-> - - * * * * - * * - - - - * * | - - - - - - * * | <-- S0
LC123-> - - - - - - - - * - - - - - - | - - - - - - - * | <-- ~748~1
Pin
83 -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- CLK
12 -> - - - - - - - - * - - - - - * | - - - - - - * * | <-- SB
11 -> - - - - - - - - * - - - - - * | - - - - - - * * | <-- SM
LC98 -> - - - - - - - * * - - - * - - | - - - - - - * * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node1
LC100-> - - - - - - - * * * * * * * - | - - - - - - * * | <-- CLR
LC97 -> - - - - - - - * * * * * * * * | - - - - - - * * | <-- EN
LC104-> - - - - - - - - * - - - - - - | - - - - - - - * | <-- ~748~2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda\hxrjtd\jtdkz.rpt
jtdkz
** EQUATIONS **
CLK : INPUT;
SB : INPUT;
SM : INPUT;
-- Node name is 'BG' = ':14'
-- Equation name is 'BG', type is output
BG = DFFE( _EQ001 $ STATE1, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = STATE0 & STATE1;
-- Node name is 'BR' = ':10'
-- Equation name is 'BR', type is output
BR = DFFE(!STATE1 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is 'BY' = ':12'
-- Equation name is 'BY', type is output
BY = DFFE( _EQ002 $ STATE0, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = STATE0 & !STATE1;
-- Node name is ':23' = 'CLR'
-- Equation name is 'CLR', location is LC100, type is buried.
CLR = DFFE( _EQ003 $ _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = CLR & EN & !_LC121 & SM & !STATE0 & STATE1 & !S0 & S1 & S2 &
S3 & _X001 & _X002 & _X003 & _X004 & _X005 & _X006 &
_X007
# CLR & EN & _LC121 & SB & !STATE0 & !STATE1 & !S0 & !S1 & !S2 &
S3 & _X001 & _X002 & _X003 & _X004 & _X005 & _X006 &
_X007;
_X001 = EXP( CLR & !EN & STATE0 & S0 & !S1 & S2 & !S3 & !S4);
_X002 = EXP( CLR & !EN & SM & !STATE0 & STATE1 & S0 & S1 & S2 & S3 & !S4);
_X003 = EXP( CLR & !EN & SB & !STATE0 & !STATE1 & S0 & !S1 & !S2 & S3 & S4);
_X004 = EXP( CLR & EN & !_LC121 & !_LC124 & STATE0 & !S0 & !S1 & S2 & !S3);
_X005 = EXP( SB & !SM & !STATE0 & !STATE1);
_X006 = EXP(!SB & !STATE0 & STATE1);
_X007 = EXP( S0 & S1 & S2);
_EQ004 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006;
_X001 = EXP( CLR & !EN & STATE0 & S0 & !S1 & S2 & !S3 & !S4);
_X002 = EXP( CLR & !EN & SM & !STATE0 & STATE1 & S0 & S1 & S2 & S3 & !S4);
_X003 = EXP( CLR & !EN & SB & !STATE0 & !STATE1 & S0 & !S1 & !S2 & S3 & S4);
_X004 = EXP( CLR & EN & !_LC121 & !_LC124 & STATE0 & !S0 & !S1 & S2 & !S3);
_X005 = EXP( SB & !SM & !STATE0 & !STATE1);
_X006 = EXP(!SB & !STATE0 & STATE1);
-- Node name is ':24' = 'EN'
-- Equation name is 'EN', location is LC097, type is buried.
EN = DFFE( _EQ005 $ _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = CLR & EN & _LC098 & _LC113 & !_LC121 & SM & !STATE0 & STATE1 &
!S0 & S3 & _X001 & _X002 & _X003 & _X005 & _X006 & _X007 &
_X008
# CLR & EN & !_LC098 & !_LC113 & _LC121 & SB & !STATE0 & !STATE1 &
!S0 & S3 & _X001 & _X002 & _X003 & _X005 & _X006 & _X007 &
_X008;
_X001 = EXP( CLR & !EN & STATE0 & S0 & !S1 & S2 & !S3 & !S4);
_X002 = EXP( CLR & !EN & SM & !STATE0 & STATE1 & S0 & S1 & S2 & S3 & !S4);
_X003 = EXP( CLR & !EN & SB & !STATE0 & !STATE1 & S0 & !S1 & !S2 & S3 & S4);
_X005 = EXP( SB & !SM & !STATE0 & !STATE1);
_X006 = EXP(!SB & !STATE0 & STATE1);
_X007 = EXP( S0 & S1 & S2);
_X008 = EXP( CLR & EN & !_LC098 & _LC113 & !_LC121 & !_LC124 & STATE0 & !S0 &
!S3);
_EQ006 = _X001 & _X002 & _X003 & _X005 & _X006 & _X008;
_X001 = EXP( CLR & !EN & STATE0 & S0 & !S1 & S2 & !S3 & !S4);
_X002 = EXP( CLR & !EN & SM & !STATE0 & STATE1 & S0 & S1 & S2 & S3 & !S4);
_X003 = EXP( CLR & !EN & SB & !STATE0 & !STATE1 & S0 & !S1 & !S2 & S3 & S4);
_X005 = EXP( SB & !SM & !STATE0 & !STATE1);
_X006 = EXP(!SB & !STATE0 & STATE1);
_X008 = EXP( CLR & EN & !_LC098 & _LC113 & !_LC121 & !_LC124 & STATE0 & !S0 &
!S3);
-- Node name is 'MG' = ':8'
-- Equation name is 'MG', type is output
MG = DFFE( _EQ007 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = !STATE0 & !STATE1;
-- Node name is 'MR' = ':4'
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