📄 xskz.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY XSKZ IS
PORT(EN25,EN15,EN5M,EN5B:IN STD_LOGIC;
AIN25M,AIN25B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
AIN15M,AIN15B,AIN5:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTM,DOUTB: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY XSKZ;
ARCHITECTURE one OF XSKZ IS
BEGIN
PROCESS(EN25,EN15,EN5M,EN5B) IS
BEGIN
IF EN25='1' THEN
DOUTM<=AIN25M(7 DOWNTO 0);DOUTB<=AIN25B(7 DOWNTO 0);
ELSIF EN5M='1' THEN
DOUTM<=AIN5(7 DOWNTO 0);DOUTB<=AIN5(7 DOWNTO 0);
ELSIF EN15='1' THEN
DOUTM<=AIN15M(7 DOWNTO 0);DOUTB<=AIN15B(7 DOWNTO 0);
ELSIF EN5B='1' THEN
DOUTM<=AIN5(7 DOWNTO 0);DOUTB<=AIN5(7 DOWNTO 0);
END IF;
END PROCESS;
END ARCHITECTURE one;
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