📄 hxrjtd.qsf
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# Copyright (C) 1991-2004 Altera Corporation
# Any megafunction design, and related netlist (encrypted or decrypted),
# support information, device programming or simulation file, and any other
# associated documentation or information provided by Altera or a partner
# under Altera's Megafunction Partnership Program may be used only
# to program PLD devices (but not masked PLD devices) from Altera. Any
# other use of such megafunction design, netlist, support information,
# device programming or simulation file, or any other related documentation
# or information is prohibited for any other purpose, including, but not
# limited to modification, reverse engineering, de-compiling, or use with
# any other silicon devices, unless such use is explicitly licensed under
# a separate agreement with Altera or a megafunction partner. Title to the
# intellectual property, including patents, copyrights, trademarks, trade
# secrets, or maskworks, embodied in any such megafunction design, netlist,
# support information, device programming or simulation file, or any other
# related documentation or information provided by Altera or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.
# The default values for assignments are stored in the file
# hxrjtd_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:05:03 MAY 24, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 4.1
set_global_assignment -name VHDL_FILE cnt15.vhd
set_global_assignment -name VHDL_FILE cnt25.vhd
set_global_assignment -name VHDL_FILE cnt5.vhd
set_global_assignment -name VHDL_FILE fpj.vhd
set_global_assignment -name VHDL_FILE jtdkz.vhd
set_global_assignment -name GDF_FILE nn.gdf
set_global_assignment -name VHDL_FILE xskz.vhd
# Pin & Location Assignments
# ==========================
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
set_location_assignment PIN_204 -to BG
set_location_assignment PIN_206 -to BR
set_location_assignment PIN_205 -to BY
set_location_assignment PIN_181 -to CLK
set_location_assignment PIN_54 -to DOUTB\[0\]
set_location_assignment PIN_55 -to DOUTB\[1\]
set_location_assignment PIN_125 -to DOUTB\[2\]
set_location_assignment PIN_126 -to DOUTB\[3\]
set_location_assignment PIN_129 -to DOUTB\[4\]
set_location_assignment PIN_130 -to DOUTB\[5\]
set_location_assignment PIN_131 -to DOUTB\[6\]
set_location_assignment PIN_133 -to DOUTB\[7\]
set_location_assignment PIN_43 -to DOUTM\[0\]
set_location_assignment PIN_44 -to DOUTM\[1\]
set_location_assignment PIN_46 -to DOUTM\[2\]
set_location_assignment PIN_47 -to DOUTM\[3\]
set_location_assignment PIN_48 -to DOUTM\[4\]
set_location_assignment PIN_49 -to DOUTM\[5\]
set_location_assignment PIN_50 -to DOUTM\[6\]
set_location_assignment PIN_53 -to DOUTM\[7\]
set_location_assignment PIN_207 -to MG
set_location_assignment PIN_41 -to MR
set_location_assignment PIN_40 -to MY
set_location_assignment PIN_16 -to RST
set_location_assignment PIN_13 -to SB
set_location_assignment PIN_11 -to SM
# Timing Assignments
# ==================
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 3
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "FPGA Express"
set_global_assignment -name FAMILY APEX20KE
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name TOP_LEVEL_ENTITY nn
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EP20K300EQC240-3"
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name OPTIMIZE_TIMING NORMAL_COMPILATION
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX NORMAL
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_instance_assignment -name IO_STANDARD LVTTL -to BG
set_instance_assignment -name IO_STANDARD LVTTL -to BR
set_instance_assignment -name IO_STANDARD LVTTL -to BY
set_instance_assignment -name IO_STANDARD LVTTL -to CLK
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTB\[0\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTB\[1\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTB\[2\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTB\[3\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTB\[4\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTB\[5\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTB\[6\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTB\[7\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTM\[0\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTM\[1\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTM\[2\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTM\[3\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTM\[4\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTM\[5\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTM\[6\]
set_instance_assignment -name IO_STANDARD LVTTL -to DOUTM\[7\]
set_instance_assignment -name IO_STANDARD LVTTL -to MG
set_instance_assignment -name IO_STANDARD LVTTL -to MR
set_instance_assignment -name IO_STANDARD LVTTL -to MY
set_instance_assignment -name IO_STANDARD LVTTL -to RST
set_instance_assignment -name IO_STANDARD LVTTL -to SB
set_instance_assignment -name IO_STANDARD LVTTL -to SM
# Timing Analysis Assignments
# ===========================
set_global_assignment -name MAX_SCC_SIZE 50
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name HARDCOPY_EXTERNAL_CLOCK_JITTER "0.0 NS"
# Assembler Assignments
# =====================
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
# Simulator Assignments
# =====================
set_global_assignment -name START_TIME 0NS
set_global_assignment -name POWER_ESTIMATION_START_TIME "0 NS"
set_global_assignment -name GLITCH_INTERVAL 1NS
# Design Assistant Assignments
# ============================
set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF
set_global_assignment -name ASSG_CAT OFF
set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF
set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF
set_global_assignment -name SIGNALRACE_RULE_TRISTATE OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF
set_global_assignment -name CLK_CAT OFF
set_global_assignment -name CLK_RULE_COMB_CLOCK OFF
set_global_assignment -name CLK_RULE_INV_CLOCK OFF
set_global_assignment -name CLK_RULE_GATING_SCHEME OFF
set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF
set_global_assignment -name CLK_RULE_MIX_EDGES OFF
set_global_assignment -name RESET_CAT OFF
set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF
set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF
set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF
set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF
set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF
set_global_assignment -name TIMING_CAT OFF
set_global_assignment -name TIMING_RULE_SHIFT_REG OFF
set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF
set_global_assignment -name NONSYNCHSTRUCT_CAT OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF
set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF
set_global_assignment -name SIGNALRACE_CAT OFF
set_global_assignment -name ACLK_CAT OFF
set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF
set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF
set_global_assignment -name HCPY_CAT OFF
set_global_assignment -name HCPY_VREF_PINS OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE fpga_exp.lmf -section_id eda_design_synthesis
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------
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