📄 nn.rpt
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Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 29/64 ( 45%)
Total logic cells used: 95/128 ( 74%)
Total shareable expanders used: 65/128 ( 50%)
Total Turbo logic cells used: 95/128 ( 74%)
Total shareable expanders not available (n/a): 20/128 ( 15%)
Average fan-in: 5.86
Total fan-in: 557
Total input pins required: 4
Total fast input logic cells required: 0
Total output pins required: 22
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 95
Total flipflops required: 28
Total product terms required: 373
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 59
Synthesized logic cells: 37/ 128 ( 28%)
Device-Specific Information: e:\hxrjtd\nn.rpt
nn
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 CLK
10 (6) (A) INPUT 0 0 0 0 0 0 1 RST
11 (5) (A) INPUT 0 0 0 0 0 0 14 SB
12 (3) (A) INPUT 0 0 0 0 0 0 9 SM
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\hxrjtd\nn.rpt
nn
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
74 117 H FF t 0 0 0 0 3 8 22 BG
70 109 G FF t 0 0 0 0 2 0 0 BR
75 118 H FF t 0 0 0 0 3 8 21 BY
41 49 D OUTPUT t 1 1 0 0 7 0 0 B0
29 38 C OUTPUT t 0 0 0 0 3 0 0 B1
28 40 C OUTPUT t 0 0 0 0 3 0 0 B2
52 80 E OUTPUT t 0 0 0 0 9 0 0 B3
58 91 F OUTPUT t 0 0 0 0 9 0 0 B4
40 51 D OUTPUT t 0 0 0 0 6 0 0 B5
44 65 E OUTPUT t 0 0 0 0 5 0 0 B6
48 72 E OUTPUT t 0 0 0 0 5 0 0 B7
73 115 H FF t 0 0 0 0 3 16 22 MG
64 99 G FF t 0 0 0 0 2 0 0 MR
63 97 G FF t 0 0 0 0 3 8 21 MY
31 35 C OUTPUT t 0 0 0 0 3 0 0 M0
35 59 D OUTPUT t 1 1 0 0 7 0 0 M1
25 45 C OUTPUT t 0 0 0 0 3 0 0 M2
39 53 D OUTPUT t 1 1 0 0 7 0 0 M3
30 37 C OUTPUT t 1 1 0 0 7 0 0 M4
56 86 F OUTPUT t 0 0 0 0 10 0 0 M5
46 69 E OUTPUT t 0 0 0 0 5 0 0 M6
45 67 E OUTPUT t 0 0 0 0 5 0 0 M7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\hxrjtd\nn.rpt
nn
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 63 D SOFT t 0 0 0 0 2 0 1 |CNT5:3|LPM_ADD_SUB:38|addcore:adder|addcore:adder0|result_node1
- 79 E SOFT t 0 0 0 0 3 0 1 |CNT5:3|LPM_ADD_SUB:38|addcore:adder|addcore:adder0|result_node2
- 60 D DFFE t 0 0 0 0 4 0 7 |CNT5:3|CNT3B2 (|CNT5:3|:12)
- 58 D DFFE t 0 0 0 0 4 0 8 |CNT5:3|CNT3B1 (|CNT5:3|:13)
(37) 56 D TFFE t 0 0 0 0 4 0 5 |CNT5:3|CNT3B0 (|CNT5:3|:14)
(60) 93 F SOFT t 0 0 0 0 2 0 1 |CNT15:1|LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node1
(61) 94 F SOFT t 0 0 0 0 3 0 1 |CNT15:1|LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node2
(62) 96 F SOFT t 0 0 0 0 4 0 1 |CNT15:1|LPM_ADD_SUB:101|addcore:adder|addcore:adder0|result_node3
(67) 104 G DFFE t 1 1 0 2 3 3 13 |CNT15:1|CNT5B3 (|CNT15:1|:21)
(68) 105 G DFFE t 1 1 0 2 3 3 14 |CNT15:1|CNT5B2 (|CNT15:1|:22)
(69) 107 G DFFE t 1 1 0 2 3 3 15 |CNT15:1|CNT5B1 (|CNT15:1|:23)
- 102 G DFFE t 1 1 0 2 3 1 11 |CNT15:1|CNT5B0 (|CNT15:1|:24)
- 36 C SOFT t 0 0 0 0 2 0 1 |CNT25:2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node1
- 92 F SOFT t 0 0 0 0 3 0 1 |CNT25:2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node2
- 95 F SOFT t 0 0 0 0 4 0 1 |CNT25:2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node3
- 87 F SOFT t 0 0 0 0 5 0 1 |CNT25:2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node4
- 103 G DFFE t 0 0 0 1 3 4 17 |CNT25:2|CNTB4 (|CNT25:2|:20)
- 108 G DFFE t 0 0 0 1 3 4 18 |CNT25:2|CNTB3 (|CNT25:2|:21)
- 100 G DFFE t 0 0 0 1 3 4 19 |CNT25:2|CNTB2 (|CNT25:2|:22)
(65) 101 G DFFE t 0 0 0 1 3 4 20 |CNT25:2|CNTB1 (|CNT25:2|:23)
- 98 G DFFE t 0 0 0 1 3 4 21 |CNT25:2|CNTB0 (|CNT25:2|:24)
- 84 F SOFT s t 1 1 0 0 5 1 0 |CNT25:2|~2001~1
(57) 88 F SOFT s t 2 1 1 0 5 1 0 |CNT25:2|~2235~1
- 89 F SOFT s t 1 1 0 0 5 1 0 |CNT25:2|~2391~1
(36) 57 D SOFT s t 1 1 0 0 5 1 0 |CNT25:2|~2625~1
(34) 61 D SOFT s t 2 1 1 0 5 1 2 |CNT25:2|~2703~1
- 41 C SOFT s t 6 2 1 0 5 1 2 |CNT25:2|~2781~1
(15) 29 B SOFT s t 7 1 1 0 5 1 1 |CNT25:2|~2859~1
- 30 B SOFT s t 8 2 1 0 5 1 1 |CNT25:2|~2937~1
- 33 C TFFE + t 0 0 0 1 0 6 21 |FPJ:4|CNTER (|FPJ:4|:4)
- 127 H SOFT t 0 0 0 0 3 0 3 |JTDKZ:5|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|gcp2
- 119 H SOFT t 0 0 0 0 2 0 4 |JTDKZ:5|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node1
- 116 H SOFT t 0 0 0 0 3 0 4 |JTDKZ:5|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node2
- 114 H SOFT t 0 0 0 0 4 0 2 |JTDKZ:5|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3
- 121 H SOFT t 0 0 0 0 5 0 6 |JTDKZ:5|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node4
- 122 H TFFE t 0 0 0 0 13 6 5 |JTDKZ:5|STATE1 (|JTDKZ:5|:16)
(77) 123 H DFFE t 13 1 0 2 15 4 6 |JTDKZ:5|STATE0 (|JTDKZ:5|:17)
- 124 H DFFE t 0 0 0 0 5 0 8 |JTDKZ:5|S4 (|JTDKZ:5|:18)
- 113 H DFFE t 0 0 0 0 5 0 8 |JTDKZ:5|S3 (|JTDKZ:5|:19)
(76) 120 H DFFE t 0 0 0 0 5 0 10 |JTDKZ:5|S2 (|JTDKZ:5|:20)
(80) 126 H DFFE t 0 0 0 0 5 0 11 |JTDKZ:5|S1 (|JTDKZ:5|:21)
(79) 125 H DFFE t 0 0 0 0 4 0 12 |JTDKZ:5|S0 (|JTDKZ:5|:22)
- 106 G DFFE t 7 6 0 2 12 0 9 |JTDKZ:5|CLR (|JTDKZ:5|:23)
(71) 112 G DFFE t 7 6 0 2 14 0 11 |JTDKZ:5|EN (|JTDKZ:5|:24)
(81) 128 H SOFT s t 1 0 1 2 8 0 1 |JTDKZ:5|~748~1
- 110 G SOFT s t 1 0 1 2 7 0 1 |JTDKZ:5|~748~2
- 66 E LCELL s t 1 0 0 0 5 1 1 |XSKZ:6|~548~1
- 78 E LCELL s t 0 0 0 0 5 1 1 |XSKZ:6|~563~1
(55) 85 F SOFT s t 0 0 0 0 8 0 1 |XSKZ:6|~575~1
- 39 C LCELL s t 2 1 1 0 7 1 1 |XSKZ:6|~578~1
(54) 83 F SOFT s t 2 0 1 0 8 1 1 |XSKZ:6|~590~1
- 34 C LCELL s t 1 1 0 0 7 0 1 |XSKZ:6|~593~1
- 81 F SOFT s t 1 0 1 0 8 1 1 |XSKZ:6|~605~1
- 52 D LCELL s t 1 1 0 0 7 0 1 |XSKZ:6|~608~1
(49) 73 E SOFT s t 6 1 1 0 10 1 1 |XSKZ:6|~620~1
(24) 46 C LCELL s t 4 1 1 0 7 0 1 |XSKZ:6|~623~1
- 55 D SOFT s t 7 1 1 0 10 1 1 |XSKZ:6|~635~1
- 50 D LCELL s t 1 1 0 0 7 0 1 |XSKZ:6|~638~1
(33) 64 D SOFT s t 5 0 0 0 11 1 1 |XSKZ:6|~650~1
- 44 C LCELL s t 2 1 1 0 7 0 1 |XSKZ:6|~653~1
(51) 77 E LCELL s t 0 0 0 0 5 1 1 |XSKZ:6|~668~1
- 74 E LCELL s t 0 0 0 0 5 1 1 |XSKZ:6|~683~1
- 62 D LCELL s t 3 1 1 0 10 1 1 |XSKZ:6|~698~1
- 90 F LCELL s t 1 0 1 0 9 0 1 |XSKZ:6|~713~1~2
- 82 F LCELL s t 1 0 1 0 10 1 2 |XSKZ:6|~713~1
- 71 E LCELL s t 0 0 0 0 8 0 1 |XSKZ:6|~728~1~2
- 70 E LCELL s t 1 0 1 0 10 1 2 |XSKZ:6|~728~1
- 68 E SOFT s t 2 1 1 0 9 1 1 |XSKZ:6|~740~1
(27) 43 C LCELL s t 0 0 0 0 3 0 1 |XSKZ:6|~743~1
- 76 E SOFT s t 3 1 1 0 9 1 1 |XSKZ:6|~755~1
- 42 C LCELL s t 0 0 0 0 3 0 1 |XSKZ:6|~758~1
(50) 75 E SOFT s t 1 0 0 0 8 1 1 |XSKZ:6|~770~1
- 54 D LCELL s t 1 1 0 0 7 0 1 |XSKZ:6|~773~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\hxrjtd\nn.rpt
nn
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--- LC29 |CNT25:2|~2859~1
| +- LC30 |CNT25:2|~2937~1
| |
| | Other LABs fed by signals
| | that feed LAB 'B'
LC | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
83 -> - - | - - - - - - - - | <-- CLK
LC103-> * * | - * * * - * - - | <-- |CNT25:2|CNTB4
LC108-> * * | - * * * - * - - | <-- |CNT25:2|CNTB3
LC100-> * * | - * * * - * - - | <-- |CNT25:2|CNTB2
LC101-> * * | - * * * - * - - | <-- |CNT25:2|CNTB1
LC98 -> * * | - * * * - * * - | <-- |CNT25:2|CNTB0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\hxrjtd\nn.rpt
nn
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+--------------------------- LC38 B1
| +------------------------- LC40 B2
| | +----------------------- LC36 |CNT25:2|LPM_ADD_SUB:109|addcore:adder|addcore:adder0|result_node1
| | | +--------------------- LC41 |CNT25:2|~2781~1
| | | | +------------------- LC33 |FPJ:4|CNTER
| | | | | +----------------- LC35 M0
| | | | | | +--------------- LC45 M2
| | | | | | | +------------- LC37 M4
| | | | | | | | +----------- LC39 |XSKZ:6|~578~1
| | | | | | | | | +--------- LC34 |XSKZ:6|~593~1
| | | | | | | | | | +------- LC46 |XSKZ:6|~623~1
| | | | | | | | | | | +----- LC44 |XSKZ:6|~653~1
| | | | | | | | | | | | +--- LC43 |XSKZ:6|~743~1
| | | | | | | | | | | | | +- LC42 |XSKZ:6|~758~1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
Pin
83 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- CLK
10 -> - - - - * - - - - - - - - - | - - * - - - - - | <-- RST
LC103-> - - - * - - - * * * * * - - | - * * * - * - - | <-- |CNT25:2|CNTB4
LC108-> - - - * - - - * * * * * - - | - * * * - * - - | <-- |CNT25:2|CNTB3
LC100-> - - - * - - - * * * * * - - | - * * * - * - - | <-- |CNT25:2|CNTB2
LC101-> - - * * - - - * * * * * - - | - * * * - * - - | <-- |CNT25:2|CNTB1
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