📄 receive.mfd

📁 结合XILINXCPLD所做的模拟RS232通信verilog源程序
💻 MFD
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	/bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N115.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N115.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK * 
	/bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N115.FBK.LFBK
;Imported pterms FB5_5
	+ /rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N115.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK * 
	/bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N115.FBK.LFBK
    "sbuf<3>".CLKF  =  clock_pluse
    "sbuf<3>".PRLD  =  VCC

MACROCELL | 4 | 4 | N118
ATTRIBUTES | 4653862 | 0
OUTPUTMC | 3 | 4 | 5 | 4 | 4 | 4 | 3
INPUTS | 16 | rxd  | bit_cnt_0.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_0.FBK.LFBK  | bit_collect_1.FBK.LFBK  | count_reg_1.FBK.LFBK  | N118.FBK.LFBK  | count_reg_2  | count_reg_3  | bit_collect_0.FBK.LFBK  | N115.FBK.LFBK  | clock_pluse  | EXP2_.EXP  | rxd_start_reg.FBK.LFBK
INPUTMC | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 13 | 4 | 4 | 2 | 14 | 2 | 13 | 4 | 17 | 4 | 5 | 2 | 7 | 4 | 3 | 4 | 15
INPUTP | 1 | 18
EXPORTS | 1 | 4 | 5
IMPORTS | 1 | 4 | 3
EQ | 35 | 
    "sbuf<4>".T  =  rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * N118.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	/bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N118.FBK.LFBK
;Imported pterms FB5_4
	+ rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N118.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N118.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N118.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	/bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N118.FBK.LFBK
    "sbuf<4>".CLKF  =  clock_pluse
    "sbuf<4>".PRLD  =  VCC
    N118.EXP  =  /rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N115.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK * 
	/bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N115.FBK.LFBK

MACROCELL | 4 | 2 | N121
ATTRIBUTES | 4653862 | 0
OUTPUTMC | 2 | 4 | 2 | 4 | 1
INPUTS | 15 | rxd  | bit_cnt_0.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_0.FBK.LFBK  | bit_collect_1.FBK.LFBK  | count_reg_1.FBK.LFBK  | N121.FBK.LFBK  | count_reg_2  | count_reg_3  | bit_collect_0.FBK.LFBK  | clock_pluse  | N124.EXP  | rxd_start_reg.FBK.LFBK
INPUTMC | 14 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 13 | 4 | 2 | 2 | 14 | 2 | 13 | 4 | 17 | 2 | 7 | 4 | 1 | 4 | 15
INPUTP | 1 | 18
IMPORTS | 1 | 4 | 1
EQ | 27 | 
    "sbuf<5>".T  =  rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * N121.FBK.LFBK
	+ rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N121.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N121.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N121.FBK.LFBK
;Imported pterms FB5_2
	+ /rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N121.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N121.FBK.LFBK
    "sbuf<5>".CLKF  =  clock_pluse
    "sbuf<5>".PRLD  =  VCC

MACROCELL | 4 | 1 | N124
ATTRIBUTES | 4653862 | 0
OUTPUTMC | 3 | 4 | 2 | 4 | 1 | 4 | 0
INPUTS | 16 | rxd  | bit_cnt_0.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_0.FBK.LFBK  | bit_collect_1.FBK.LFBK  | count_reg_1.FBK.LFBK  | N124.FBK.LFBK  | count_reg_2  | count_reg_3  | bit_collect_0.FBK.LFBK  | N121.FBK.LFBK  | clock_pluse  | EXP1_.EXP  | rxd_start_reg.FBK.LFBK
INPUTMC | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 13 | 4 | 1 | 2 | 14 | 2 | 13 | 4 | 17 | 4 | 2 | 2 | 7 | 4 | 0 | 4 | 15
INPUTP | 1 | 18
EXPORTS | 1 | 4 | 2
IMPORTS | 1 | 4 | 0
EQ | 35 | 
    "sbuf<6>".T  =  rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * N124.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N124.FBK.LFBK
;Imported pterms FB5_1
	+ rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N124.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N124.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N124.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N124.FBK.LFBK
    "sbuf<6>".CLKF  =  clock_pluse
    "sbuf<6>".PRLD  =  VCC
    N124.EXP  =  /rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N121.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N121.FBK.LFBK

MACROCELL | 2 | 16 | N127
ATTRIBUTES | 4653862 | 0
OUTPUTMC | 3 | 2 | 15 | 2 | 17 | 2 | 16
INPUTS | 16 | rxd  | rxd_start_reg  | bit_cnt_0  | bit_cnt_1  | bit_cnt_2  | bit_cnt_3  | count_reg_0  | bit_collect_1  | count_reg_1  | count_reg_3.FBK.LFBK  | N127.FBK.LFBK  | clock_pluse.FBK.LFBK  | bit_collect_0  | clock_div_1.EXP  | clock_div_2.EXP  | count_reg_2.FBK.LFBK
INPUTMC | 15 | 4 | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 13 | 2 | 13 | 2 | 16 | 2 | 7 | 4 | 17 | 2 | 15 | 2 | 17 | 2 | 14
INPUTP | 1 | 18
IMPORTS | 2 | 2 | 15 | 2 | 17
EQ | 28 | 
    "sbuf<7>".T  =  rxd * rxd_start_reg * /bit_cnt_0 * /bit_cnt_1 * 
	/bit_cnt_2 * bit_cnt_3 * count_reg_0 * bit_collect_0 * 
	count_reg_1 * count_reg_2.FBK.LFBK * /count_reg_3.FBK.LFBK * 
	N127.FBK.LFBK
	+ rxd * rxd_start_reg * /bit_cnt_0 * /bit_cnt_1 * 
	/bit_cnt_2 * bit_cnt_3 * count_reg_0 * bit_collect_1 * 
	count_reg_1 * count_reg_2.FBK.LFBK * /count_reg_3.FBK.LFBK * 
	N127.FBK.LFBK
	+ /rxd * rxd_start_reg * /bit_cnt_0 * /bit_cnt_1 * 
	/bit_cnt_2 * bit_cnt_3 * count_reg_0 * /bit_collect_1 * 
	count_reg_1 * count_reg_2.FBK.LFBK * /count_reg_3.FBK.LFBK * 
	/N127.FBK.LFBK
	+ rxd_start_reg * /bit_cnt_0 * /bit_cnt_1 * 
	/bit_cnt_2 * bit_cnt_3 * count_reg_0 * bit_collect_0 * 
	bit_collect_1 * count_reg_1 * count_reg_2.FBK.LFBK * 
	/count_reg_3.FBK.LFBK * N127.FBK.LFBK
;Imported pterms FB3_16
	+ rxd_start_reg * /bit_cnt_0 * /bit_cnt_1 * 
	/bit_cnt_2 * bit_cnt_3 * count_reg_0 * /bit_collect_0 * 
	/bit_collect_1 * count_reg_1 * count_reg_2.FBK.LFBK * 
	/count_reg_3.FBK.LFBK * /N127.FBK.LFBK
;Imported pterms FB3_18
	+ /rxd * rxd_start_reg * /bit_cnt_0 * /bit_cnt_1 * 
	/bit_cnt_2 * bit_cnt_3 * count_reg_0 * /bit_collect_0 * 
	count_reg_1 * count_reg_2.FBK.LFBK * /count_reg_3.FBK.LFBK * 
	/N127.FBK.LFBK
    "sbuf<7>".CLKF  =  clock_pluse.FBK.LFBK
    "sbuf<7>".PRLD  =  VCC

MACROCELL | 2 | 0 | EXP0_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 2 | 17
INPUTS | 3 | clock_div_3.FBK.LFBK  | clock_div_2.FBK.LFBK  | clock_div_6.FBK.LFBK
INPUTMC | 3 | 2 | 12 | 2 | 17 | 2 | 8
EXPORTS | 1 | 2 | 17
EQ | 2 | 
       EXP0_.EXP  =  clock_div_6.FBK.LFBK * clock_div_3.FBK.LFBK * 
	clock_div_2.FBK.LFBK

MACROCELL | 4 | 0 | EXP1_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 4 | 1
INPUTS | 13 | rxd  | bit_cnt_0.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_0.FBK.LFBK  | bit_collect_0.FBK.LFBK  | count_reg_1.FBK.LFBK  | N124.FBK.LFBK  | count_reg_2  | count_reg_3  | bit_collect_1.FBK.LFBK  | rxd_start_reg.FBK.LFBK
INPUTMC | 12 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 17 | 4 | 13 | 4 | 1 | 2 | 14 | 2 | 13 | 4 | 16 | 4 | 15
INPUTP | 1 | 18
EXPORTS | 1 | 4 | 1
EQ | 16 | 
       EXP1_.EXP  =  rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N124.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N124.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N124.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N124.FBK.LFBK

MACROCELL | 4 | 3 | EXP2_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 4 | 4
INPUTS | 13 | rxd  | bit_cnt_0.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_0.FBK.LFBK  | bit_collect_0.FBK.LFBK  | count_reg_1.FBK.LFBK  | N118.FBK.LFBK  | count_reg_2  | count_reg_3  | bit_collect_1.FBK.LFBK  | rxd_start_reg.FBK.LFBK
INPUTMC | 12 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 17 | 4 | 13 | 4 | 4 | 2 | 14 | 2 | 13 | 4 | 16 | 4 | 15
INPUTP | 1 | 18
EXPORTS | 1 | 4 | 4
EQ | 16 | 
       EXP2_.EXP  =  rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N118.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N118.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N118.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	/bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N118.FBK.LFBK

PIN | rxd | 0 | 1 | 64 | 21 | 4 | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 13 | 4 | 17 | 4 | 0 | 4 | 3 | 2 | 14 | 2 | 13 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 5 | 4 | 4 | 4 | 2 | 4 | 1 | 2 | 16 | 2 | 17 | 4 | 16
PIN | clock | 0 | 11 | 4096 | 8 | 2 | 7 | 2 | 8 | 2 | 11 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 15 | 2 | 17
PIN | sbuf<0> | 4 | 10 | 536871040
PIN | sbuf<1> | 4 | 8 | 536871040
PIN | sbuf<2> | 4 | 7 | 536871040
PIN | sbuf<3> | 4 | 5 | 536871040
PIN | sbuf<4> | 4 | 4 | 536871040
PIN | sbuf<5> | 4 | 2 | 536871040
PIN | sbuf<6> | 4 | 1 | 536871040
PIN | sbuf<7> | 2 | 16 | 536871040
上一页 1 23
💿 文件大小 119 K
👤 上传用户 xiazaichongchon
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#XILINXCPLD #verilog #232 #RS
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