receive.mfd

结合XILINXCPLD所做的模拟RS232通信verilog源程序

	count_reg_1.FBK.LFBK

MACROCELL | 2 | 14 | count_reg_2
ATTRIBUTES | 4391712 | 0
OUTPUTMC | 22 | 4 | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 13 | 4 | 17 | 4 | 0 | 4 | 3 | 4 | 16 | 4 | 1 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 5 | 4 | 4 | 4 | 2 | 2 | 14 | 2 | 13 | 2 | 15 | 2 | 17 | 2 | 16
INPUTS | 7 | rxd_start_reg  | count_reg_0  | count_reg_1  | rxd  | count_reg_3.FBK.LFBK  | clock_pluse.FBK.LFBK  | count_reg_2.FBK.LFBK
INPUTMC | 6 | 4 | 15 | 4 | 14 | 4 | 13 | 2 | 13 | 2 | 7 | 2 | 14
INPUTP | 1 | 18
EQ | 6 | 
    count_reg_2.T  =  /rxd * /rxd_start_reg * count_reg_2.FBK.LFBK
	+ rxd_start_reg * count_reg_0 * count_reg_1
	+ rxd_start_reg * count_reg_1 * 
	count_reg_2.FBK.LFBK * count_reg_3.FBK.LFBK
    count_reg_2.CLKF  =  clock_pluse.FBK.LFBK
    count_reg_2.PRLD  =  GND

MACROCELL | 2 | 11 | clock_div_0
ATTRIBUTES | 8618752 | 0
OUTPUTMC | 7 | 2 | 8 | 2 | 11 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 15 | 2 | 17
INPUTS | 5 | clock_div_0.FBK.LFBK  | clock_div_3.FBK.LFBK  | clock_div_4.FBK.LFBK  | clock_div_5.FBK.LFBK  | clock_div_6.FBK.LFBK
INPUTMC | 5 | 2 | 11 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 8
EQ | 5 | 
    clock_div_0  :=  /clock_div_6.FBK.LFBK * /clock_div_0.FBK.LFBK
	+ /clock_div_3.FBK.LFBK * /clock_div_4.FBK.LFBK * 
	/clock_div_5.FBK.LFBK * /clock_div_0.FBK.LFBK
    clock_div_0.CLKF  =  /clock	;FCLK/GCK
    clock_div_0.PRLD  =  GND
GLOBALS | 1 | 2 | clock

MACROCELL | 2 | 12 | clock_div_3
ATTRIBUTES | 4424448 | 0
OUTPUTMC | 9 | 2 | 7 | 2 | 8 | 2 | 11 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 15 | 2 | 17 | 2 | 0
INPUTS | 7 | clock_div_4.FBK.LFBK  | clock_div_5.FBK.LFBK  | clock_div_1.FBK.LFBK  | clock_div_2.FBK.LFBK  | clock_div_6.FBK.LFBK  | clock_div_3.FBK.LFBK  | clock_div_0.FBK.LFBK
INPUTMC | 7 | 2 | 10 | 2 | 9 | 2 | 15 | 2 | 17 | 2 | 8 | 2 | 12 | 2 | 11
EQ | 7 | 
    clock_div_3.T  =  clock_div_6.FBK.LFBK * clock_div_3.FBK.LFBK
	+ /clock_div_6.FBK.LFBK * clock_div_0.FBK.LFBK * 
	clock_div_1.FBK.LFBK * clock_div_2.FBK.LFBK
	+ /clock_div_4.FBK.LFBK * /clock_div_5.FBK.LFBK * 
	clock_div_0.FBK.LFBK * clock_div_1.FBK.LFBK * clock_div_2.FBK.LFBK
    clock_div_3.CLKF  =  /clock	;FCLK/GCK
    clock_div_3.PRLD  =  GND
GLOBALS | 1 | 2 | clock

MACROCELL | 2 | 10 | clock_div_4
ATTRIBUTES | 4424448 | 0
OUTPUTMC | 8 | 2 | 7 | 2 | 8 | 2 | 11 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 15 | 2 | 17
INPUTS | 6 | clock_div_0.FBK.LFBK  | clock_div_3.FBK.LFBK  | clock_div_1.FBK.LFBK  | clock_div_2.FBK.LFBK  | clock_div_4.FBK.LFBK  | clock_div_6.FBK.LFBK
INPUTMC | 6 | 2 | 11 | 2 | 12 | 2 | 15 | 2 | 17 | 2 | 10 | 2 | 8
EQ | 5 | 
    clock_div_4.T  =  clock_div_6.FBK.LFBK * clock_div_4.FBK.LFBK
	+ /clock_div_6.FBK.LFBK * clock_div_3.FBK.LFBK * 
	clock_div_0.FBK.LFBK * clock_div_1.FBK.LFBK * clock_div_2.FBK.LFBK
    clock_div_4.CLKF  =  /clock	;FCLK/GCK
    clock_div_4.PRLD  =  GND
GLOBALS | 1 | 2 | clock

MACROCELL | 2 | 9 | clock_div_5
ATTRIBUTES | 4424448 | 0
OUTPUTMC | 7 | 2 | 7 | 2 | 8 | 2 | 11 | 2 | 12 | 2 | 9 | 2 | 15 | 2 | 17
INPUTS | 7 | clock_div_0.FBK.LFBK  | clock_div_3.FBK.LFBK  | clock_div_4.FBK.LFBK  | clock_div_1.FBK.LFBK  | clock_div_2.FBK.LFBK  | clock_div_5.FBK.LFBK  | clock_div_6.FBK.LFBK
INPUTMC | 7 | 2 | 11 | 2 | 12 | 2 | 10 | 2 | 15 | 2 | 17 | 2 | 9 | 2 | 8
EQ | 6 | 
    clock_div_5.T  =  clock_div_6.FBK.LFBK * clock_div_5.FBK.LFBK
	+ /clock_div_6.FBK.LFBK * clock_div_3.FBK.LFBK * 
	clock_div_4.FBK.LFBK * clock_div_0.FBK.LFBK * clock_div_1.FBK.LFBK * 
	clock_div_2.FBK.LFBK
    clock_div_5.CLKF  =  /clock	;FCLK/GCK
    clock_div_5.PRLD  =  GND
GLOBALS | 1 | 2 | clock

MACROCELL | 2 | 13 | count_reg_3
ATTRIBUTES | 4391712 | 0
OUTPUTMC | 22 | 4 | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 13 | 4 | 17 | 4 | 0 | 4 | 3 | 4 | 16 | 4 | 1 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 5 | 4 | 4 | 4 | 2 | 2 | 14 | 2 | 13 | 2 | 15 | 2 | 17 | 2 | 16
INPUTS | 7 | rxd_start_reg  | count_reg_0  | count_reg_1  | count_reg_3.FBK.LFBK  | rxd  | clock_pluse.FBK.LFBK  | count_reg_2.FBK.LFBK
INPUTMC | 6 | 4 | 15 | 4 | 14 | 4 | 13 | 2 | 13 | 2 | 7 | 2 | 14
INPUTP | 1 | 18
EQ | 7 | 
    count_reg_3.T  =  /rxd * /rxd_start_reg * count_reg_3.FBK.LFBK
	+ rxd_start_reg * count_reg_0 * count_reg_1 * 
	count_reg_2.FBK.LFBK
	+ rxd_start_reg * count_reg_1 * 
	count_reg_2.FBK.LFBK * count_reg_3.FBK.LFBK
    count_reg_3.CLKF  =  clock_pluse.FBK.LFBK
    count_reg_3.PRLD  =  GND

MACROCELL | 2 | 15 | clock_div_1
ATTRIBUTES | 8618752 | 0
OUTPUTMC | 7 | 2 | 16 | 2 | 8 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 15 | 2 | 17
INPUTS | 18 | clock_div_0.FBK.LFBK  | clock_div_1.FBK.LFBK  | clock_div_3.FBK.LFBK  | clock_div_4.FBK.LFBK  | clock_div_5.FBK.LFBK  | count_reg_2.FBK.LFBK  | rxd_start_reg  | bit_cnt_0  | bit_cnt_1  | bit_cnt_2  | bit_cnt_3  | count_reg_0  | bit_collect_0  | bit_collect_1  | count_reg_1  | count_reg_3.FBK.LFBK  | N127.FBK.LFBK  | clock_div_6.FBK.LFBK
INPUTMC | 18 | 2 | 11 | 2 | 15 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 14 | 4 | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 17 | 4 | 16 | 4 | 13 | 2 | 13 | 2 | 16 | 2 | 8
EXPORTS | 1 | 2 | 16
EQ | 14 | 
    clock_div_1  :=  /clock_div_6.FBK.LFBK * clock_div_0.FBK.LFBK * 
	/clock_div_1.FBK.LFBK
	+ /clock_div_6.FBK.LFBK * /clock_div_0.FBK.LFBK * 
	clock_div_1.FBK.LFBK
	+ /clock_div_3.FBK.LFBK * /clock_div_4.FBK.LFBK * 
	/clock_div_5.FBK.LFBK * clock_div_0.FBK.LFBK * /clock_div_1.FBK.LFBK
	+ /clock_div_3.FBK.LFBK * /clock_div_4.FBK.LFBK * 
	/clock_div_5.FBK.LFBK * /clock_div_0.FBK.LFBK * clock_div_1.FBK.LFBK
    clock_div_1.CLKF  =  /clock	;FCLK/GCK
    clock_div_1.PRLD  =  GND
    clock_div_1.EXP  =  rxd_start_reg * /bit_cnt_0 * /bit_cnt_1 * 
	/bit_cnt_2 * bit_cnt_3 * count_reg_0 * /bit_collect_0 * 
	/bit_collect_1 * count_reg_1 * count_reg_2.FBK.LFBK * 
	/count_reg_3.FBK.LFBK * /N127.FBK.LFBK
GLOBALS | 1 | 2 | clock

MACROCELL | 2 | 17 | clock_div_2
ATTRIBUTES | 4424448 | 0
OUTPUTMC | 7 | 2 | 16 | 2 | 8 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 17 | 2 | 0
INPUTS | 20 | clock_div_3.FBK.LFBK  | clock_div_4.FBK.LFBK  | clock_div_5.FBK.LFBK  | clock_div_1.FBK.LFBK  | clock_div_6.FBK.LFBK  | clock_div_2.FBK.LFBK  | count_reg_2.FBK.LFBK  | rxd  | rxd_start_reg  | bit_cnt_0  | bit_cnt_1  | bit_cnt_2  | bit_cnt_3  | count_reg_0  | bit_collect_0  | count_reg_1  | count_reg_3.FBK.LFBK  | N127.FBK.LFBK  | EXP0_.EXP  | clock_div_0.FBK.LFBK
INPUTMC | 19 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 15 | 2 | 8 | 2 | 17 | 2 | 14 | 4 | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 17 | 4 | 13 | 2 | 13 | 2 | 16 | 2 | 0 | 2 | 11
INPUTP | 1 | 18
EXPORTS | 1 | 2 | 16
IMPORTS | 1 | 2 | 0
EQ | 17 | 
    clock_div_2.T  =  clock_div_6.FBK.LFBK * clock_div_4.FBK.LFBK * 
	clock_div_2.FBK.LFBK
	+ clock_div_6.FBK.LFBK * clock_div_5.FBK.LFBK * 
	clock_div_2.FBK.LFBK
	+ /clock_div_6.FBK.LFBK * clock_div_0.FBK.LFBK * 
	clock_div_1.FBK.LFBK
	+ /clock_div_3.FBK.LFBK * /clock_div_4.FBK.LFBK * 
	/clock_div_5.FBK.LFBK * clock_div_0.FBK.LFBK * clock_div_1.FBK.LFBK
;Imported pterms FB3_1
	+ clock_div_6.FBK.LFBK * clock_div_3.FBK.LFBK * 
	clock_div_2.FBK.LFBK
    clock_div_2.CLKF  =  /clock	;FCLK/GCK
    clock_div_2.PRLD  =  GND
    clock_div_2.EXP  =  /rxd * rxd_start_reg * /bit_cnt_0 * /bit_cnt_1 * 
	/bit_cnt_2 * bit_cnt_3 * count_reg_0 * /bit_collect_0 * 
	count_reg_1 * count_reg_2.FBK.LFBK * /count_reg_3.FBK.LFBK * 
	/N127.FBK.LFBK
GLOBALS | 1 | 2 | clock

MACROCELL | 4 | 10 | N106
ATTRIBUTES | 4653862 | 0
OUTPUTMC | 2 | 4 | 11 | 4 | 10
INPUTS | 15 | rxd  | bit_cnt_0.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_0.FBK.LFBK  | bit_collect_1.FBK.LFBK  | count_reg_1.FBK.LFBK  | N106.FBK.LFBK  | count_reg_2  | count_reg_3  | bit_collect_0.FBK.LFBK  | clock_pluse  | bit_cnt_1.EXP  | rxd_start_reg.FBK.LFBK
INPUTMC | 14 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 13 | 4 | 10 | 2 | 14 | 2 | 13 | 4 | 17 | 2 | 7 | 4 | 11 | 4 | 15
INPUTP | 1 | 18
IMPORTS | 1 | 4 | 11
EQ | 27 | 
    "sbuf<0>".T  =  rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * N106.FBK.LFBK
	+ rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N106.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N106.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	/bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N106.FBK.LFBK
;Imported pterms FB5_12
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N106.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	/bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N106.FBK.LFBK
    "sbuf<0>".CLKF  =  clock_pluse
    "sbuf<0>".PRLD  =  VCC

MACROCELL | 4 | 8 | N109
ATTRIBUTES | 4653862 | 0
OUTPUTMC | 2 | 4 | 9 | 4 | 8
INPUTS | 15 | rxd  | bit_cnt_0.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_0.FBK.LFBK  | bit_collect_1.FBK.LFBK  | count_reg_1.FBK.LFBK  | N109.FBK.LFBK  | count_reg_2  | count_reg_3  | bit_collect_0.FBK.LFBK  | clock_pluse  | bit_cnt_2.EXP  | rxd_start_reg.FBK.LFBK
INPUTMC | 14 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 13 | 4 | 8 | 2 | 14 | 2 | 13 | 4 | 17 | 2 | 7 | 4 | 9 | 4 | 15
INPUTP | 1 | 18
IMPORTS | 1 | 4 | 9
EQ | 27 | 
    "sbuf<1>".T  =  rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * N109.FBK.LFBK
	+ rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N109.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N109.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N109.FBK.LFBK
;Imported pterms FB5_10
	+ /rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N109.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N109.FBK.LFBK
    "sbuf<1>".CLKF  =  clock_pluse
    "sbuf<1>".PRLD  =  VCC

MACROCELL | 4 | 7 | N112
ATTRIBUTES | 4653862 | 0
OUTPUTMC | 2 | 4 | 6 | 4 | 7
INPUTS | 15 | rxd  | bit_cnt_0.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_0.FBK.LFBK  | bit_collect_1.FBK.LFBK  | count_reg_1.FBK.LFBK  | N112.FBK.LFBK  | count_reg_2  | count_reg_3  | bit_collect_0.FBK.LFBK  | clock_pluse  | bit_cnt_3.EXP  | rxd_start_reg.FBK.LFBK
INPUTMC | 14 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 13 | 4 | 7 | 2 | 14 | 2 | 13 | 4 | 17 | 2 | 7 | 4 | 6 | 4 | 15
INPUTP | 1 | 18
IMPORTS | 1 | 4 | 6
EQ | 27 | 
    "sbuf<2>".T  =  rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * N112.FBK.LFBK
	+ rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N112.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N112.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * N112.FBK.LFBK
;Imported pterms FB5_7
	+ /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N112.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N112.FBK.LFBK
    "sbuf<2>".CLKF  =  clock_pluse
    "sbuf<2>".PRLD  =  VCC

MACROCELL | 4 | 5 | N115
ATTRIBUTES | 4653862 | 0
OUTPUTMC | 2 | 4 | 5 | 4 | 4
INPUTS | 15 | rxd  | bit_cnt_0.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_0.FBK.LFBK  | bit_collect_1.FBK.LFBK  | count_reg_1.FBK.LFBK  | N115.FBK.LFBK  | count_reg_2  | count_reg_3  | bit_collect_0.FBK.LFBK  | clock_pluse  | N118.EXP  | rxd_start_reg.FBK.LFBK
INPUTMC | 14 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 13 | 4 | 5 | 2 | 14 | 2 | 13 | 4 | 17 | 2 | 7 | 4 | 4 | 4 | 15
INPUTP | 1 | 18
IMPORTS | 1 | 4 | 4
EQ | 27 | 
    "sbuf<3>".T  =  rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK * N115.FBK.LFBK
	+ rxd * count_reg_2 * /count_reg_3 *