📄 receive.mfd

📁 结合XILINXCPLD所做的模拟RS232通信verilog源程序
💻 MFD
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字号:
12 3 下一页
MDF Database:  version 1.0
MDF_INFO | receive | XC95108-7-PC84
MACROCELL | 2 | 7 | clock_pluse
ATTRIBUTES | 8618752 | 0
OUTPUTMC | 19 | 4 | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 17 | 4 | 16 | 4 | 13 | 4 | 2 | 4 | 1 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 5 | 4 | 4 | 2 | 14 | 2 | 13 | 2 | 16
INPUTS | 4 | clock_div_3.FBK.LFBK  | clock_div_4.FBK.LFBK  | clock_div_5.FBK.LFBK  | clock_div_6.FBK.LFBK
INPUTMC | 4 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 8
EQ | 5 | 
   /clock_pluse  :=  /clock_div_6.FBK.LFBK
	+ /clock_div_3.FBK.LFBK * /clock_div_4.FBK.LFBK * 
	/clock_div_5.FBK.LFBK
    clock_pluse.CLKF  =  /clock	;FCLK/GCK
    clock_pluse.PRLD  =  GND
GLOBALS | 1 | 2 | clock

MACROCELL | 4 | 15 | rxd_start_reg
ATTRIBUTES | 8586016 | 0
OUTPUTMC | 23 | 2 | 14 | 2 | 13 | 2 | 17 | 2 | 15 | 2 | 16 | 4 | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 17 | 4 | 16 | 4 | 13 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 5 | 4 | 4 | 4 | 2 | 4 | 1 | 4 | 0 | 4 | 3
INPUTS | 15 | rxd  | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_0.FBK.LFBK  | bit_collect_1.FBK.LFBK  | count_reg_1.FBK.LFBK  | bit_collect_0.FBK.LFBK  | count_reg_2  | count_reg_3  | rxd_start_reg.FBK.LFBK  | clock_pluse  | count_reg_0.EXP  | bit_collect_1.EXP  | bit_cnt_0.FBK.LFBK
INPUTMC | 14 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 13 | 4 | 17 | 2 | 14 | 2 | 13 | 4 | 15 | 2 | 7 | 4 | 14 | 4 | 16 | 4 | 12
INPUTP | 1 | 18
IMPORTS | 2 | 4 | 14 | 4 | 16
EQ | 34 | 
   /rxd_start_reg  :=  /bit_cnt_0.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	/bit_cnt_2.FBK.LFBK * bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * 
	count_reg_1.FBK.LFBK
	+ rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK
;Imported pterms FB5_15
	+ bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ bit_cnt_1.FBK.LFBK * bit_cnt_3.FBK.LFBK * 
	/count_reg_0.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ bit_cnt_1.FBK.LFBK * bit_cnt_3.FBK.LFBK * 
	/count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
;Imported pterms FB5_17
	+ rxd * /rxd_start_reg.FBK.LFBK
	+ /count_reg_2 * bit_cnt_1.FBK.LFBK * 
	bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ count_reg_3 * bit_cnt_1.FBK.LFBK * 
	bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK * 
	/bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK
    rxd_start_reg.CLKF  =  clock_pluse
    rxd_start_reg.PRLD  =  GND

MACROCELL | 4 | 12 | bit_cnt_0
ATTRIBUTES | 4391712 | 0
OUTPUTMC | 19 | 2 | 16 | 2 | 17 | 2 | 15 | 4 | 13 | 4 | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 16 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 5 | 4 | 4 | 4 | 2 | 4 | 1 | 4 | 0 | 4 | 3
INPUTS | 8 | rxd  | bit_cnt_0.FBK.LFBK  | count_reg_0.FBK.LFBK  | count_reg_1.FBK.LFBK  | count_reg_2  | count_reg_3  | clock_pluse  | rxd_start_reg.FBK.LFBK
INPUTMC | 7 | 4 | 12 | 4 | 14 | 4 | 13 | 2 | 14 | 2 | 13 | 2 | 7 | 4 | 15
INPUTP | 1 | 18
EXPORTS | 1 | 4 | 13
EQ | 10 | 
    bit_cnt_0.T  =  /rxd * bit_cnt_0.FBK.LFBK * 
	/rxd_start_reg.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * count_reg_0.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK
    bit_cnt_0.CLKF  =  clock_pluse
    bit_cnt_0.PRLD  =  GND
    bit_cnt_0.EXP  =  /rxd * count_reg_1.FBK.LFBK * 
	/rxd_start_reg.FBK.LFBK
	+ count_reg_2 * count_reg_3 * count_reg_1.FBK.LFBK * 
	rxd_start_reg.FBK.LFBK

MACROCELL | 4 | 11 | bit_cnt_1
ATTRIBUTES | 4391712 | 0
OUTPUTMC | 18 | 2 | 15 | 2 | 17 | 2 | 16 | 4 | 10 | 4 | 15 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 8 | 4 | 7 | 4 | 5 | 4 | 4 | 4 | 2 | 4 | 1 | 4 | 0 | 4 | 3
INPUTS | 14 | bit_cnt_0.FBK.LFBK  | count_reg_0.FBK.LFBK  | count_reg_1.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | count_reg_2  | count_reg_3  | rxd  | bit_cnt_2.FBK.LFBK  | clock_pluse  | bit_cnt_3.FBK.LFBK  | bit_collect_0.FBK.LFBK  | N106.FBK.LFBK  | bit_collect_1.FBK.LFBK  | rxd_start_reg.FBK.LFBK
INPUTMC | 13 | 4 | 12 | 4 | 14 | 4 | 13 | 4 | 11 | 2 | 14 | 2 | 13 | 4 | 9 | 2 | 7 | 4 | 6 | 4 | 17 | 4 | 10 | 4 | 16 | 4 | 15
INPUTP | 1 | 18
EXPORTS | 1 | 4 | 10
EQ | 14 | 
    bit_cnt_1.T  =  /rxd * bit_cnt_1.FBK.LFBK * 
	/rxd_start_reg.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK
    bit_cnt_1.CLKF  =  clock_pluse
    bit_cnt_1.PRLD  =  GND
    bit_cnt_1.EXP  =  /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * /bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N106.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	/bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N106.FBK.LFBK

MACROCELL | 4 | 9 | bit_cnt_2
ATTRIBUTES | 4391712 | 0
OUTPUTMC | 18 | 2 | 17 | 2 | 16 | 2 | 15 | 4 | 8 | 4 | 15 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 10 | 4 | 7 | 4 | 5 | 4 | 4 | 4 | 2 | 4 | 1 | 4 | 0 | 4 | 3
INPUTS | 14 | bit_cnt_0.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | count_reg_0.FBK.LFBK  | count_reg_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | count_reg_2  | count_reg_3  | rxd  | bit_cnt_3.FBK.LFBK  | clock_pluse  | bit_collect_0.FBK.LFBK  | N109.FBK.LFBK  | bit_collect_1.FBK.LFBK  | rxd_start_reg.FBK.LFBK
INPUTMC | 13 | 4 | 12 | 4 | 11 | 4 | 14 | 4 | 13 | 4 | 9 | 2 | 14 | 2 | 13 | 4 | 6 | 2 | 7 | 4 | 17 | 4 | 8 | 4 | 16 | 4 | 15
INPUTP | 1 | 18
EXPORTS | 1 | 4 | 8
EQ | 15 | 
    bit_cnt_2.T  =  /rxd * bit_cnt_2.FBK.LFBK * 
	/rxd_start_reg.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	rxd_start_reg.FBK.LFBK
    bit_cnt_2.CLKF  =  clock_pluse
    bit_cnt_2.PRLD  =  GND
    bit_cnt_2.EXP  =  /rxd * count_reg_2 * /count_reg_3 * 
	/bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N109.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N109.FBK.LFBK

MACROCELL | 4 | 6 | bit_cnt_3
ATTRIBUTES | 4391712 | 0
OUTPUTMC | 18 | 2 | 16 | 2 | 15 | 2 | 17 | 4 | 7 | 4 | 15 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 16 | 4 | 10 | 4 | 8 | 4 | 5 | 4 | 4 | 4 | 2 | 4 | 1 | 4 | 0 | 4 | 3
INPUTS | 14 | bit_cnt_0.FBK.LFBK  | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | count_reg_0.FBK.LFBK  | count_reg_1.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_2  | count_reg_3  | rxd  | bit_collect_0.FBK.LFBK  | clock_pluse  | N112.FBK.LFBK  | bit_collect_1.FBK.LFBK  | rxd_start_reg.FBK.LFBK
INPUTMC | 13 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 14 | 4 | 13 | 4 | 6 | 2 | 14 | 2 | 13 | 4 | 17 | 2 | 7 | 4 | 7 | 4 | 16 | 4 | 15
INPUTP | 1 | 18
EXPORTS | 1 | 4 | 7
EQ | 15 | 
    bit_cnt_3.T  =  /rxd * bit_cnt_3.FBK.LFBK * 
	/rxd_start_reg.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * count_reg_0.FBK.LFBK * 
	count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK
    bit_cnt_3.CLKF  =  clock_pluse
    bit_cnt_3.PRLD  =  GND
    bit_cnt_3.EXP  =  /rxd * count_reg_2 * /count_reg_3 * 
	bit_cnt_0.FBK.LFBK * bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	/bit_cnt_3.FBK.LFBK * count_reg_0.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N112.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * bit_cnt_0.FBK.LFBK * 
	bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	/bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK * /N112.FBK.LFBK

MACROCELL | 4 | 14 | count_reg_0
ATTRIBUTES | 4391712 | 0
OUTPUTMC | 23 | 2 | 14 | 2 | 13 | 2 | 17 | 2 | 15 | 2 | 16 | 4 | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 17 | 4 | 16 | 4 | 13 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 5 | 4 | 4 | 4 | 2 | 4 | 1 | 4 | 0 | 4 | 3
INPUTS | 8 | bit_cnt_1.FBK.LFBK  | bit_cnt_2.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | count_reg_0.FBK.LFBK  | count_reg_1.FBK.LFBK  | clock_pluse  | count_reg_1.EXP  | rxd_start_reg.FBK.LFBK
INPUTMC | 8 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 14 | 4 | 13 | 2 | 7 | 4 | 13 | 4 | 15
EXPORTS | 1 | 4 | 15
IMPORTS | 1 | 4 | 13
EQ | 15 | 
   /count_reg_0.T  =  ;Imported pterms FB5_14
	  rxd * /rxd_start_reg.FBK.LFBK
	+ /count_reg_0.FBK.LFBK * /rxd_start_reg.FBK.LFBK
	+ count_reg_2 * count_reg_3 * /count_reg_0.FBK.LFBK * 
	count_reg_1.FBK.LFBK
    count_reg_0.CLKF  =  clock_pluse
    count_reg_0.PRLD  =  GND
    count_reg_0.EXP  =  bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * 
	bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ bit_cnt_1.FBK.LFBK * bit_cnt_3.FBK.LFBK * 
	/count_reg_0.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ bit_cnt_1.FBK.LFBK * bit_cnt_3.FBK.LFBK * 
	/count_reg_1.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ /bit_cnt_1.FBK.LFBK * bit_cnt_2.FBK.LFBK * 
	bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK

MACROCELL | 4 | 17 | bit_collect_0
ATTRIBUTES | 4391712 | 0
OUTPUTMC | 18 | 2 | 16 | 2 | 15 | 2 | 17 | 4 | 16 | 4 | 15 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 17 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 5 | 4 | 4 | 4 | 2 | 4 | 1 | 4 | 0 | 4 | 3
INPUTS | 9 | rxd  | count_reg_0.FBK.LFBK  | bit_collect_0.FBK.LFBK  | count_reg_1.FBK.LFBK  | bit_collect_1.FBK.LFBK  | count_reg_2  | count_reg_3  | clock_pluse  | rxd_start_reg.FBK.LFBK
INPUTMC | 8 | 4 | 14 | 4 | 17 | 4 | 13 | 4 | 16 | 2 | 14 | 2 | 13 | 2 | 7 | 4 | 15
INPUTP | 1 | 18
EXPORTS | 1 | 4 | 16
EQ | 14 | 
    bit_collect_0.T  =  rxd * count_reg_2 * /count_reg_3 * 
	count_reg_0.FBK.LFBK * /count_reg_1.FBK.LFBK * /bit_collect_0.FBK.LFBK * 
	rxd_start_reg.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	count_reg_0.FBK.LFBK * /count_reg_1.FBK.LFBK * bit_collect_0.FBK.LFBK * 
	rxd_start_reg.FBK.LFBK
    bit_collect_0.CLKF  =  clock_pluse
    bit_collect_0.PRLD  =  GND
    bit_collect_0.EXP  =  rxd * count_reg_2 * /count_reg_3 * 
	/count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	rxd_start_reg.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	/count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	rxd_start_reg.FBK.LFBK

MACROCELL | 4 | 16 | bit_collect_1
ATTRIBUTES | 4391712 | 0
OUTPUTMC | 17 | 2 | 15 | 2 | 16 | 4 | 15 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 17 | 4 | 16 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 5 | 4 | 4 | 4 | 2 | 4 | 1 | 4 | 0 | 4 | 3
INPUTS | 14 | rxd  | bit_cnt_1.FBK.LFBK  | bit_cnt_3.FBK.LFBK  | bit_cnt_0.FBK.LFBK  | count_reg_2  | count_reg_3  | bit_cnt_2.FBK.LFBK  | clock_pluse  | count_reg_0.FBK.LFBK  | bit_collect_0.FBK.LFBK  | bit_collect_1.FBK.LFBK  | count_reg_1.FBK.LFBK  | bit_collect_0.EXP  | rxd_start_reg.FBK.LFBK
INPUTMC | 13 | 4 | 11 | 4 | 6 | 4 | 12 | 2 | 14 | 2 | 13 | 4 | 9 | 2 | 7 | 4 | 14 | 4 | 17 | 4 | 16 | 4 | 13 | 4 | 17 | 4 | 15
INPUTP | 1 | 18
EXPORTS | 1 | 4 | 15
IMPORTS | 1 | 4 | 17
EQ | 18 | 
    bit_collect_1.T  =  ;Imported pterms FB5_18
	  rxd * count_reg_2 * /count_reg_3 * 
	/count_reg_0.FBK.LFBK * /bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	rxd_start_reg.FBK.LFBK
	+ /rxd * count_reg_2 * /count_reg_3 * 
	/count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	rxd_start_reg.FBK.LFBK
    bit_collect_1.CLKF  =  clock_pluse
    bit_collect_1.PRLD  =  GND
    bit_collect_1.EXP  =  rxd * /rxd_start_reg.FBK.LFBK
	+ /count_reg_2 * bit_cnt_1.FBK.LFBK * 
	bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ count_reg_3 * bit_cnt_1.FBK.LFBK * 
	bit_cnt_3.FBK.LFBK * rxd_start_reg.FBK.LFBK
	+ count_reg_2 * /count_reg_3 * /bit_cnt_0.FBK.LFBK * 
	/bit_cnt_1.FBK.LFBK * /bit_cnt_2.FBK.LFBK * /bit_cnt_3.FBK.LFBK * 
	count_reg_0.FBK.LFBK * bit_collect_1.FBK.LFBK * count_reg_1.FBK.LFBK * 
	bit_collect_0.FBK.LFBK * rxd_start_reg.FBK.LFBK

MACROCELL | 2 | 8 | clock_div_6
ATTRIBUTES | 8618752 | 0
OUTPUTMC | 9 | 2 | 7 | 2 | 8 | 2 | 11 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 15 | 2 | 17 | 2 | 0
INPUTS | 7 | clock_div_3.FBK.LFBK  | clock_div_4.FBK.LFBK  | clock_div_5.FBK.LFBK  | clock_div_0.FBK.LFBK  | clock_div_1.FBK.LFBK  | clock_div_2.FBK.LFBK  | clock_div_6.FBK.LFBK
INPUTMC | 7 | 2 | 12 | 2 | 10 | 2 | 9 | 2 | 11 | 2 | 15 | 2 | 17 | 2 | 8
EQ | 7 | 
    clock_div_6  :=  clock_div_6.FBK.LFBK * /clock_div_3.FBK.LFBK * 
	/clock_div_4.FBK.LFBK * /clock_div_5.FBK.LFBK
	+ /clock_div_6.FBK.LFBK * clock_div_3.FBK.LFBK * 
	clock_div_4.FBK.LFBK * clock_div_5.FBK.LFBK * clock_div_0.FBK.LFBK * 
	clock_div_1.FBK.LFBK * clock_div_2.FBK.LFBK
    clock_div_6.CLKF  =  /clock	;FCLK/GCK
    clock_div_6.PRLD  =  GND
GLOBALS | 1 | 2 | clock

MACROCELL | 4 | 13 | count_reg_1
ATTRIBUTES | 4391712 | 0
OUTPUTMC | 23 | 2 | 14 | 2 | 13 | 2 | 17 | 2 | 15 | 2 | 16 | 4 | 14 | 4 | 15 | 4 | 12 | 4 | 11 | 4 | 9 | 4 | 6 | 4 | 17 | 4 | 16 | 4 | 13 | 4 | 10 | 4 | 8 | 4 | 7 | 4 | 5 | 4 | 4 | 4 | 2 | 4 | 1 | 4 | 0 | 4 | 3
INPUTS | 8 | count_reg_0.FBK.LFBK  | count_reg_1.FBK.LFBK  | rxd  | count_reg_2  | count_reg_3  | clock_pluse  | bit_cnt_0.EXP  | rxd_start_reg.FBK.LFBK
INPUTMC | 7 | 4 | 14 | 4 | 13 | 2 | 14 | 2 | 13 | 2 | 7 | 4 | 12 | 4 | 15
INPUTP | 1 | 18
EXPORTS | 1 | 4 | 14
IMPORTS | 1 | 4 | 12
EQ | 12 | 
    count_reg_1.T  =  count_reg_0.FBK.LFBK * rxd_start_reg.FBK.LFBK
;Imported pterms FB5_13
	+ /rxd * count_reg_1.FBK.LFBK * 
	/rxd_start_reg.FBK.LFBK
	+ count_reg_2 * count_reg_3 * count_reg_1.FBK.LFBK * 
	rxd_start_reg.FBK.LFBK
    count_reg_1.CLKF  =  clock_pluse
    count_reg_1.PRLD  =  GND
    count_reg_1.EXP  =  rxd * /rxd_start_reg.FBK.LFBK
	+ /count_reg_0.FBK.LFBK * /rxd_start_reg.FBK.LFBK
	+ count_reg_2 * count_reg_3 * /count_reg_0.FBK.LFBK *
12 3 下一页
💿 文件大小 119 K
👤 上传用户 xiazaichongchon
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#XILINXCPLD #verilog #232 #RS
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