receive.vm6

结合XILINXCPLD所做的模拟RS232通信verilog源程序

SPPTERM | 4 | IV_FALSE | count_reg_2 | IV_TRUE | bit_cnt_1.FBK | IV_TRUE | bit_cnt_3.FBK | IV_TRUE | rxd_start_reg.FBK
SPPTERM | 4 | IV_TRUE | count_reg_3 | IV_TRUE | bit_cnt_1.FBK | IV_TRUE | bit_cnt_3.FBK | IV_TRUE | rxd_start_reg.FBK
SPPTERM | 11 | IV_TRUE | count_reg_2 | IV_FALSE | count_reg_3 | IV_FALSE | bit_cnt_0.FBK | IV_FALSE | bit_cnt_1.FBK | IV_FALSE | bit_cnt_2.FBK | IV_FALSE | bit_cnt_3.FBK | IV_TRUE | count_reg_0.FBK | IV_TRUE | bit_collect_1.FBK | IV_TRUE | count_reg_1.FBK | IV_TRUE | bit_collect_0.FBK | IV_TRUE | rxd_start_reg.FBK

SRFF_INSTANCE | bit_collect_1.REG | bit_collect_1 | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | bit_collect_1.D | 3371 | ? | 0 | 0 | bit_collect_1 | NULL | NULL | bit_collect_1.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | bit_collect_1.CLKF | 3374 | ? | 0 | 4096 | bit_collect_1 | NULL | NULL | bit_collect_1.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | bit_collect_1.Q | 3375 | ? | 0 | 0 | bit_collect_1 | NULL | NULL | bit_collect_1.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+OptxMapped+ClkInv | clock_div_6 | receive_COPY_0_COPY_0 | 2222982144 | 8 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_3.FBK | 3490 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_3.Q | clock_div_3 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_4.FBK | 3491 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_4.Q | clock_div_4 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_5.FBK | 3492 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_5.Q | clock_div_5 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_0.FBK | 3505 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_0.Q | clock_div_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_1.FBK | 3506 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_1.Q | clock_div_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_2.FBK | 3507 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_2.Q | clock_div_2 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | FCLK-IO_0 | 3286 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N143 | 7 | 5 | II_FCLKINV
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_6.FBK | 3489 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_6.Q | clock_div_6 | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | clock_div_6 | 3296 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_6.Q | clock_div_6 | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | clock_div_6.FBK | 3489 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_6.Q | clock_div_6 | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | clock_div_6.SI | clock_div_6 | 0 | 7 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_3.FBK | 3490 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_3.Q | clock_div_3 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_4.FBK | 3491 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_4.Q | clock_div_4 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_5.FBK | 3492 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_5.Q | clock_div_5 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_0.FBK | 3505 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_0.Q | clock_div_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_1.FBK | 3506 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_1.Q | clock_div_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_2.FBK | 3507 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_2.Q | clock_div_2 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_div_6.FBK | 3489 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_div_6.Q | clock_div_6 | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | clock_div_6.D1 | 3377 | ? | 0 | 4096 | clock_div_6 | NULL | NULL | clock_div_6.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | clock_div_6.D2 | 3378 | ? | 0 | 4096 | clock_div_6 | NULL | NULL | clock_div_6.SI | 2 | 9 | MC_SI_D2
SPPTERM | 4 | IV_TRUE | clock_div_6.FBK | IV_FALSE | clock_div_3.FBK | IV_FALSE | clock_div_4.FBK | IV_FALSE | clock_div_5.FBK
SPPTERM | 7 | IV_FALSE | clock_div_6.FBK | IV_TRUE | clock_div_3.FBK | IV_TRUE | clock_div_4.FBK | IV_TRUE | clock_div_5.FBK | IV_TRUE | clock_div_0.FBK | IV_TRUE | clock_div_1.FBK | IV_TRUE | clock_div_2.FBK

SRFF_INSTANCE | clock_div_6.REG | clock_div_6 | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | clock_div_6.D | 3376 | ? | 0 | 0 | clock_div_6 | NULL | NULL | clock_div_6.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
NODE | FCLK-IO_0 | 3286 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N143 | 7 | 5 | II_FCLKINV
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | clock_div_6.Q | 3379 | ? | 0 | 0 | clock_div_6 | NULL | NULL | clock_div_6.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+ClkInv | count_reg_1 | receive_COPY_0_COPY_0 | 2222986240 | 8 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N272 | 3285 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N272 | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_2 | 3298 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_3 | 3303 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_3.Q | count_reg_3 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse | 3287 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_0.EXP | 3484 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_0.EXP | bit_cnt_0 | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg.FBK | 3501 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | count_reg_1 | 3297 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | count_reg_1.EXP | 3485 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.EXP | count_reg_1 | 4 | 0 | MC_EXPORT
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | count_reg_1.SI | count_reg_1 | 0 | 8 | 4
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N272 | 3285 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N272 | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_2 | 3298 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_3 | 3303 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_3.Q | count_reg_3 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse | 3287 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_0.EXP | 3484 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_0.EXP | bit_cnt_0 | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg.FBK | 3501 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | count_reg_1.D1 | 3381 | ? | 0 | 4096 | count_reg_1 | NULL | NULL | count_reg_1.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | count_reg_1.D2 | 3382 | ? | 0 | 4096 | count_reg_1 | NULL | NULL | count_reg_1.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | bit_cnt_0.EXP
SPPTERM | 2 | IV_TRUE | count_reg_0.FBK | IV_TRUE | rxd_start_reg.FBK
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | count_reg_1.CLKF | 3383 | ? | 0 | 4096 | count_reg_1 | NULL | NULL | count_reg_1.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | count_reg_1.EXP | 3473 | ? | 0 | 0 | count_reg_1 | NULL | NULL | count_reg_1.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 2 | IV_TRUE | N272 | IV_FALSE | rxd_start_reg.FBK
SPPTERM | 2 | IV_FALSE | count_reg_0.FBK | IV_FALSE | rxd_start_reg.FBK
SPPTERM | 4 | IV_TRUE | count_reg_2 | IV_TRUE | count_reg_3 | IV_FALSE | count_reg_0.FBK | IV_TRUE | count_reg_1.FBK

SRFF_INSTANCE | count_reg_1.REG | count_reg_1 | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | count_reg_1.D | 3380 | ? | 0 | 0 | count_reg_1 | NULL | NULL | count_reg_1.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | count_reg_1.CLKF | 3383 | ? | 0 | 4096 | count_reg_1 | NULL | NULL | count_reg_1.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | count_reg_1.Q | 3384 | ? | 0 | 0 | count_reg_1 | NULL | NULL | count_reg_1.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+ClkInv | count_reg_2 | receive_COPY_0_COPY_0 | 2222986240 | 7 | 2
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg | 3288 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0 | 3293 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1 | 3297 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N272 | 3285 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N272 | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_3.FBK | 3509 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_3.Q | count_reg_3 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse.FBK | 3510 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_2.FBK | 3508 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | count_reg_2 | 3298 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | count_reg_2.FBK | 3508 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | count_reg_2.SI | count_reg_2 | 0 | 7 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg | 3288 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0 | 3293 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1 | 3297 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N272 | 3285 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N272 | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_3.FBK | 3509 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_3.Q | count_reg_3 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse.FBK | 3510 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_2.FBK | 3508 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | count_reg_2.D1 | 3386 | ? | 0 | 4096 | count_reg_2 | NULL | NULL | count_reg_2.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | count_reg_2.D2 | 3387 | ? | 0 | 4096 | count_reg_2 | NULL | NULL