receive.vm6

结合XILINXCPLD所做的模拟RS232通信verilog源程序

NODE | count_reg_1.EXP | 3485 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.EXP | count_reg_1 | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg.FBK | 3501 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | count_reg_0.D1 | 3362 | ? | 0 | 4096 | count_reg_0 | NULL | NULL | count_reg_0.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | count_reg_0.D2 | 3363 | ? | 0 | 4096 | count_reg_0 | NULL | NULL | count_reg_0.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | count_reg_1.EXP
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | count_reg_0.CLKF | 3364 | ? | 0 | 4096 | count_reg_0 | NULL | NULL | count_reg_0.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | count_reg_0.EXP | 3474 | ? | 0 | 0 | count_reg_0 | NULL | NULL | count_reg_0.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 4 | IV_TRUE | bit_cnt_1.FBK | IV_FALSE | bit_cnt_2.FBK | IV_TRUE | bit_cnt_3.FBK | IV_TRUE | rxd_start_reg.FBK
SPPTERM | 4 | IV_TRUE | bit_cnt_1.FBK | IV_TRUE | bit_cnt_3.FBK | IV_FALSE | count_reg_0.FBK | IV_TRUE | rxd_start_reg.FBK
SPPTERM | 4 | IV_TRUE | bit_cnt_1.FBK | IV_TRUE | bit_cnt_3.FBK | IV_FALSE | count_reg_1.FBK | IV_TRUE | rxd_start_reg.FBK
SPPTERM | 4 | IV_FALSE | bit_cnt_1.FBK | IV_TRUE | bit_cnt_2.FBK | IV_TRUE | bit_cnt_3.FBK | IV_TRUE | rxd_start_reg.FBK

SRFF_INSTANCE | count_reg_0.REG | count_reg_0 | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | count_reg_0.D | 3361 | ? | 0 | 0 | count_reg_0 | NULL | NULL | count_reg_0.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | count_reg_0.CLKF | 3364 | ? | 0 | 4096 | count_reg_0 | NULL | NULL | count_reg_0.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | count_reg_0.Q | 3365 | ? | 0 | 0 | count_reg_0 | NULL | NULL | count_reg_0.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+ClkInv | bit_collect_0 | receive_COPY_0_COPY_0 | 2222986240 | 9 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N272 | 3285 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N272 | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_0.FBK | 3500 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.Q | bit_collect_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_1.FBK | 3498 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_1.Q | bit_collect_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_2 | 3298 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_3 | 3303 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_3.Q | count_reg_3 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse | 3287 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg.FBK | 3501 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | bit_collect_0 | 3294 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.Q | bit_collect_0 | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | bit_collect_0.EXP | 3488 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.EXP | bit_collect_0 | 4 | 0 | MC_EXPORT
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | bit_collect_0.FBK | 3500 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.Q | bit_collect_0 | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | bit_collect_0.SI | bit_collect_0 | 0 | 9 | 4
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N272 | 3285 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N272 | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_0.FBK | 3500 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.Q | bit_collect_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_1.FBK | 3498 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_1.Q | bit_collect_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_2 | 3298 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_3 | 3303 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_3.Q | count_reg_3 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse | 3287 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg.FBK | 3501 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | bit_collect_0.D1 | 3367 | ? | 0 | 4096 | bit_collect_0 | NULL | NULL | bit_collect_0.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | bit_collect_0.D2 | 3368 | ? | 0 | 4096 | bit_collect_0 | NULL | NULL | bit_collect_0.SI | 2 | 9 | MC_SI_D2
SPPTERM | 7 | IV_TRUE | N272 | IV_TRUE | count_reg_2 | IV_FALSE | count_reg_3 | IV_TRUE | count_reg_0.FBK | IV_FALSE | count_reg_1.FBK | IV_FALSE | bit_collect_0.FBK | IV_TRUE | rxd_start_reg.FBK
SPPTERM | 7 | IV_FALSE | N272 | IV_TRUE | count_reg_2 | IV_FALSE | count_reg_3 | IV_TRUE | count_reg_0.FBK | IV_FALSE | count_reg_1.FBK | IV_TRUE | bit_collect_0.FBK | IV_TRUE | rxd_start_reg.FBK
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | bit_collect_0.CLKF | 3369 | ? | 0 | 4096 | bit_collect_0 | NULL | NULL | bit_collect_0.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | bit_collect_0.EXP | 3476 | ? | 0 | 0 | bit_collect_0 | NULL | NULL | bit_collect_0.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 7 | IV_TRUE | N272 | IV_TRUE | count_reg_2 | IV_FALSE | count_reg_3 | IV_FALSE | count_reg_0.FBK | IV_FALSE | bit_collect_1.FBK | IV_TRUE | count_reg_1.FBK | IV_TRUE | rxd_start_reg.FBK
SPPTERM | 7 | IV_FALSE | N272 | IV_TRUE | count_reg_2 | IV_FALSE | count_reg_3 | IV_FALSE | count_reg_0.FBK | IV_TRUE | bit_collect_1.FBK | IV_TRUE | count_reg_1.FBK | IV_TRUE | rxd_start_reg.FBK

SRFF_INSTANCE | bit_collect_0.REG | bit_collect_0 | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | bit_collect_0.D | 3366 | ? | 0 | 0 | bit_collect_0 | NULL | NULL | bit_collect_0.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | bit_collect_0.CLKF | 3369 | ? | 0 | 4096 | bit_collect_0 | NULL | NULL | bit_collect_0.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | bit_collect_0.Q | 3370 | ? | 0 | 0 | bit_collect_0 | NULL | NULL | bit_collect_0.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+ClkInv | bit_collect_1 | receive_COPY_0_COPY_0 | 2222986240 | 14 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N272 | 3285 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N272 | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_1.FBK | 3494 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_1.Q | bit_cnt_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_3.FBK | 3496 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_3.Q | bit_cnt_3 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_0.FBK | 3493 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_0.Q | bit_cnt_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_2 | 3298 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_3 | 3303 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_3.Q | count_reg_3 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_2.FBK | 3495 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_2.Q | bit_cnt_2 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse | 3287 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_0.FBK | 3500 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.Q | bit_collect_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_1.FBK | 3498 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_1.Q | bit_collect_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_0.EXP | 3488 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.EXP | bit_collect_0 | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg.FBK | 3501 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | bit_collect_1 | 3295 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_1.Q | bit_collect_1 | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | bit_collect_1.EXP | 3487 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_1.EXP | bit_collect_1 | 4 | 0 | MC_EXPORT
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | bit_collect_1.FBK | 3498 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_1.Q | bit_collect_1 | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | bit_collect_1.SI | bit_collect_1 | 0 | 14 | 4
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N272 | 3285 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N272 | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_1.FBK | 3494 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_1.Q | bit_cnt_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_3.FBK | 3496 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_3.Q | bit_cnt_3 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_0.FBK | 3493 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_0.Q | bit_cnt_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_2 | 3298 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_3 | 3303 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_3.Q | count_reg_3 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_2.FBK | 3495 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_2.Q | bit_cnt_2 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse | 3287 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_0.FBK | 3500 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.Q | bit_collect_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_1.FBK | 3498 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_1.Q | bit_collect_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_0.EXP | 3488 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.EXP | bit_collect_0 | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg.FBK | 3501 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | bit_collect_1.D1 | 3372 | ? | 0 | 4096 | bit_collect_1 | NULL | NULL | bit_collect_1.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | bit_collect_1.D2 | 3373 | ? | 0 | 4096 | bit_collect_1 | NULL | NULL | bit_collect_1.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | bit_collect_0.EXP
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | bit_collect_1.CLKF | 3374 | ? | 0 | 4096 | bit_collect_1 | NULL | NULL | bit_collect_1.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | bit_collect_1.EXP | 3475 | ? | 0 | 0 | bit_collect_1 | NULL | NULL | bit_collect_1.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 2 | IV_TRUE | N272 | IV_FALSE | rxd_start_reg.FBK