receive.vm6

结合XILINXCPLD所做的模拟RS232通信verilog源程序

NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_2.FBK | 3495 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_2.Q | bit_cnt_2 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_2 | 3298 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_3 | 3303 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_3.Q | count_reg_3 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N272 | 3285 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N272 | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_3.FBK | 3496 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_3.Q | bit_cnt_3 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse | 3287 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_0.FBK | 3500 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.Q | bit_collect_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N109.FBK | 3503 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | N109.Q | N109 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_1.FBK | 3498 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_1.Q | bit_collect_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg.FBK | 3501 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | bit_cnt_2.D1 | 3352 | ? | 0 | 4096 | bit_cnt_2 | NULL | NULL | bit_cnt_2.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | bit_cnt_2.D2 | 3353 | ? | 0 | 4096 | bit_cnt_2 | NULL | NULL | bit_cnt_2.SI | 2 | 9 | MC_SI_D2
SPPTERM | 3 | IV_FALSE | N272 | IV_TRUE | bit_cnt_2.FBK | IV_FALSE | rxd_start_reg.FBK
SPPTERM | 7 | IV_TRUE | count_reg_2 | IV_FALSE | count_reg_3 | IV_TRUE | bit_cnt_0.FBK | IV_TRUE | bit_cnt_1.FBK | IV_TRUE | count_reg_0.FBK | IV_TRUE | count_reg_1.FBK | IV_TRUE | rxd_start_reg.FBK
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | bit_cnt_2.CLKF | 3354 | ? | 0 | 4096 | bit_cnt_2 | NULL | NULL | bit_cnt_2.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | bit_cnt_2.EXP | 3470 | ? | 0 | 0 | bit_cnt_2 | NULL | NULL | bit_cnt_2.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 12 | IV_FALSE | N272 | IV_TRUE | count_reg_2 | IV_FALSE | count_reg_3 | IV_FALSE | bit_cnt_0.FBK | IV_TRUE | bit_cnt_1.FBK | IV_FALSE | bit_cnt_2.FBK | IV_FALSE | bit_cnt_3.FBK | IV_TRUE | count_reg_0.FBK | IV_TRUE | count_reg_1.FBK | IV_FALSE | bit_collect_0.FBK | IV_TRUE | rxd_start_reg.FBK | IV_FALSE | N109.FBK
SPPTERM | 12 | IV_TRUE | count_reg_2 | IV_FALSE | count_reg_3 | IV_FALSE | bit_cnt_0.FBK | IV_TRUE | bit_cnt_1.FBK | IV_FALSE | bit_cnt_2.FBK | IV_FALSE | bit_cnt_3.FBK | IV_TRUE | count_reg_0.FBK | IV_FALSE | bit_collect_1.FBK | IV_TRUE | count_reg_1.FBK | IV_FALSE | bit_collect_0.FBK | IV_TRUE | rxd_start_reg.FBK | IV_FALSE | N109.FBK

SRFF_INSTANCE | bit_cnt_2.REG | bit_cnt_2 | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | bit_cnt_2.D | 3351 | ? | 0 | 0 | bit_cnt_2 | NULL | NULL | bit_cnt_2.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | bit_cnt_2.CLKF | 3354 | ? | 0 | 4096 | bit_cnt_2 | NULL | NULL | bit_cnt_2.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | bit_cnt_2.Q | 3355 | ? | 0 | 0 | bit_cnt_2 | NULL | NULL | bit_cnt_2.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+ClkInv | bit_cnt_3 | receive_COPY_0_COPY_0 | 2222986240 | 14 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_0.FBK | 3493 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_0.Q | bit_cnt_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_1.FBK | 3494 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_1.Q | bit_cnt_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_2.FBK | 3495 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_2.Q | bit_cnt_2 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_3.FBK | 3496 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_3.Q | bit_cnt_3 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_2 | 3298 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_3 | 3303 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_3.Q | count_reg_3 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N272 | 3285 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N272 | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_0.FBK | 3500 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.Q | bit_collect_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse | 3287 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N112.FBK | 3504 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | N112.Q | N112 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_1.FBK | 3498 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_1.Q | bit_collect_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg.FBK | 3501 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | bit_cnt_3 | 3292 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_3.Q | bit_cnt_3 | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | bit_cnt_3.EXP | 3481 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_3.EXP | bit_cnt_3 | 4 | 0 | MC_EXPORT
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | bit_cnt_3.FBK | 3496 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_3.Q | bit_cnt_3 | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | bit_cnt_3.SI | bit_cnt_3 | 0 | 14 | 4
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_0.FBK | 3493 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_0.Q | bit_cnt_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_1.FBK | 3494 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_1.Q | bit_cnt_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_2.FBK | 3495 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_2.Q | bit_cnt_2 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_3.FBK | 3496 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_3.Q | bit_cnt_3 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_2 | 3298 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_2.Q | count_reg_2 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_3 | 3303 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_3.Q | count_reg_3 | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N272 | 3285 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | NULL | N272 | 0 | 5 | II_IMUX
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_0.FBK | 3500 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_0.Q | bit_collect_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse | 3287 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | N112.FBK | 3504 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | N112.Q | N112 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_collect_1.FBK | 3498 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_collect_1.Q | bit_collect_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg.FBK | 3501 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | bit_cnt_3.D1 | 3357 | ? | 0 | 4096 | bit_cnt_3 | NULL | NULL | bit_cnt_3.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | bit_cnt_3.D2 | 3358 | ? | 0 | 4096 | bit_cnt_3 | NULL | NULL | bit_cnt_3.SI | 2 | 9 | MC_SI_D2
SPPTERM | 3 | IV_FALSE | N272 | IV_TRUE | bit_cnt_3.FBK | IV_FALSE | rxd_start_reg.FBK
SPPTERM | 8 | IV_TRUE | count_reg_2 | IV_FALSE | count_reg_3 | IV_TRUE | bit_cnt_0.FBK | IV_TRUE | bit_cnt_1.FBK | IV_TRUE | bit_cnt_2.FBK | IV_TRUE | count_reg_0.FBK | IV_TRUE | count_reg_1.FBK | IV_TRUE | rxd_start_reg.FBK
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | bit_cnt_3.CLKF | 3359 | ? | 0 | 4096 | bit_cnt_3 | NULL | NULL | bit_cnt_3.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT
SIGNAL | NODE | bit_cnt_3.EXP | 3469 | ? | 0 | 0 | bit_cnt_3 | NULL | NULL | bit_cnt_3.SI | 7 | 9 | MC_SI_EXPORT
SPPTERM | 12 | IV_FALSE | N272 | IV_TRUE | count_reg_2 | IV_FALSE | count_reg_3 | IV_TRUE | bit_cnt_0.FBK | IV_TRUE | bit_cnt_1.FBK | IV_FALSE | bit_cnt_2.FBK | IV_FALSE | bit_cnt_3.FBK | IV_TRUE | count_reg_0.FBK | IV_TRUE | count_reg_1.FBK | IV_FALSE | bit_collect_0.FBK | IV_TRUE | rxd_start_reg.FBK | IV_FALSE | N112.FBK
SPPTERM | 12 | IV_TRUE | count_reg_2 | IV_FALSE | count_reg_3 | IV_TRUE | bit_cnt_0.FBK | IV_TRUE | bit_cnt_1.FBK | IV_FALSE | bit_cnt_2.FBK | IV_FALSE | bit_cnt_3.FBK | IV_TRUE | count_reg_0.FBK | IV_FALSE | bit_collect_1.FBK | IV_TRUE | count_reg_1.FBK | IV_FALSE | bit_collect_0.FBK | IV_TRUE | rxd_start_reg.FBK | IV_FALSE | N112.FBK

SRFF_INSTANCE | bit_cnt_3.REG | bit_cnt_3 | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | bit_cnt_3.D | 3356 | ? | 0 | 0 | bit_cnt_3 | NULL | NULL | bit_cnt_3.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | bit_cnt_3.CLKF | 3359 | ? | 0 | 4096 | bit_cnt_3 | NULL | NULL | bit_cnt_3.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clock_pluse
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | bit_cnt_3.Q | 3360 | ? | 0 | 0 | bit_cnt_3 | NULL | NULL | bit_cnt_3.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | Inv+PrldLow+Tff+OptxMapped+ClkInv | count_reg_0 | receive_COPY_0_COPY_0 | 2222986496 | 8 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_1.FBK | 3494 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_1.Q | bit_cnt_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_2.FBK | 3495 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_2.Q | bit_cnt_2 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_3.FBK | 3496 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_3.Q | bit_cnt_3 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse | 3287 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.EXP | 3485 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.EXP | count_reg_1 | 4 | 0 | MC_EXPORT
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | rxd_start_reg.FBK | 3501 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | rxd_start_reg.Q | rxd_start_reg | 5 | 0 | MC_FBK
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | count_reg_0 | 3293 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT
NODE | count_reg_0.EXP | 3486 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.EXP | count_reg_0 | 4 | 0 | MC_EXPORT
OUTPUT_NODE_TYPE | 5 | 0 | MC_FBK
NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK

SIGNAL_INSTANCE | count_reg_0.SI | count_reg_0 | 0 | 8 | 4
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_1.FBK | 3494 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_1.Q | bit_cnt_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_2.FBK | 3495 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_2.Q | bit_cnt_2 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | bit_cnt_3.FBK | 3496 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | bit_cnt_3.Q | bit_cnt_3 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_0.FBK | 3497 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_0.Q | count_reg_0 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | count_reg_1.FBK | 3499 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | count_reg_1.Q | count_reg_1 | 5 | 0 | MC_FBK
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clock_pluse | 3287 | ? | 0 | 0 | receive_COPY_0_COPY_0 | NULL | clock_pluse.Q | clock_pluse | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE