latch_case.v

来自「verilog实现锁存器」· Verilog 代码 · 共 25 行

module latch_case(
	a,
	b,
	sel_a,
	sel_b,
	y
	);

input	a, b;
input	sel_a, sel_b;
output	y;

reg		y;

always @(a or b or sel_a or sel_b)
begin
	case({sel_a, sel_b})
		2'b10 : y = a;
		2'b01 : y = b;
		default : y = a;
	endcase
end

endmodule