dff_feedback.v

来自「verilog实现锁存器」· Verilog 代码 · 共 21 行

module dff_feedback(
	clk,
	ena,
	d,
	q
	);

input	clk, ena, d;
output	q;

reg		q;

always @(posedge clk)
begin
	if(ena)
		q <= d;
end

endmodule