latch_mux.v

来自「verilog实现锁存器」· Verilog 代码 · 共 28 行

module latch_mux(
	data_in,
	ena,
	data_out
	);

input	[3:0]	data_in;
input			ena;
output	[3:0]	data_out;

//wire	[3:0]	data_out;

//assign	data_out = ena ? data_in : data_out;

reg		[3:0]	data_out;

always @(ena or data_in)
begin
	if(ena)
		data_out = data_in;
	else
		data_out = 4'h0;
end


endmodule