latch_feedback.v

来自「verilog实现锁存器」· Verilog 代码 · 共 16 行

module latch_feadback(
	c1,
	c2,
	data_in,
	data_out
	);

input	c1;
input	c2;
input[1:0]	data_in;
output[1:0]	data_out;

assign	data_out = c1 ? (c2 ? data_in : data_out) : 2'bzz;

endmodule