📄 phyuz.rpt
字号:
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - - -- INPUT ^ 0 0 0 9 phaa
124 - - - -- INPUT ^ 0 0 0 1 phab
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\lisha\phyuz.rpt
phyuz
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
102 - - A -- OUTPUT 0 1 0 0 clr_in2
112 - - - 04 OUTPUT 0 1 0 0 pha0
101 - - A -- OUTPUT 0 1 0 0 pha1
100 - - A -- OUTPUT 0 1 0 0 pha2
7 - - A -- OUTPUT 0 1 0 0 pha3
8 - - A -- OUTPUT 0 1 0 0 pha4
73 - - - 01 OUTPUT 0 1 0 0 pha5
109 - - - 01 OUTPUT 0 1 0 0 pha6
110 - - - 02 OUTPUT 0 1 0 0 pha7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\lisha\phyuz.rpt
phyuz
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 07 AND2 0 3 0 3 |LPM_ADD_SUB:143|addcore:adder|:125
- 4 - A 04 AND2 0 2 0 1 |LPM_ADD_SUB:143|addcore:adder|:129
- 5 - A 08 AND2 0 3 0 3 |LPM_ADD_SUB:143|addcore:adder|:133
- 2 - A 01 AND2 0 2 0 1 |LPM_ADD_SUB:143|addcore:adder|:137
- 4 - A 01 OR2 0 4 0 1 |LPM_ADD_SUB:143|addcore:adder|:155
- 5 - A 04 OR2 0 3 0 1 |LPM_ADD_SUB:184|addcore:adder|pcarry3
- 4 - A 02 AND2 0 2 0 1 |LPM_ADD_SUB:184|addcore:adder|:125
- 2 - A 09 OR2 0 4 0 3 |LPM_ADD_SUB:184|addcore:adder|:133
- 5 - A 01 AND2 0 2 0 1 |LPM_ADD_SUB:184|addcore:adder|:137
- 7 - A 01 OR2 0 4 0 1 |LPM_ADD_SUB:184|addcore:adder|:155
- 3 - A 01 DFFE 1 4 1 3 acc7 (:13)
- 6 - A 01 DFFE 0 3 1 4 acc6 (:14)
- 1 - A 02 DFFE 0 3 1 6 acc5 (:15)
- 7 - A 04 DFFE 0 3 1 4 acc4 (:16)
- 5 - A 02 DFFE 0 3 1 6 acc3 (:17)
- 8 - A 03 DFFE 0 3 1 6 acc2 (:18)
- 6 - A 05 DFFE 1 3 1 5 acc1 (:19)
- 1 - A 03 DFFE 1 2 1 3 acc0 (:20)
- 1 - A 04 OR2 0 4 0 8 :64
- 3 - A 04 OR2 s 0 3 0 1 ~74~1
- 1 - A 01 OR2 1 3 0 1 :222
- 2 - A 02 OR2 1 3 0 1 :231
- 2 - A 04 OR2 1 3 0 1 :240
- 3 - A 02 OR2 1 3 0 1 :249
- 2 - A 03 OR2 1 3 0 1 :258
- 1 - A 06 OR2 2 0 1 8 :360
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\lisha\phyuz.rpt
phyuz
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/144( 1%) 13/ 72( 18%) 0/ 72( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\lisha\phyuz.rpt
phyuz
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 9 :360
Device-Specific Information: f:\lisha\phyuz.rpt
phyuz
** EQUATIONS **
phaa : INPUT;
phab : INPUT;
-- Node name is ':20' = 'acc0'
-- Equation name is 'acc0', location is LC1_A3, type is buried.
acc0 = DFFE( _EQ001, _LC1_A6, VCC, VCC, VCC);
_EQ001 = acc0 & _LC1_A4 & !phaa
# !acc0 & _LC1_A4 & phaa;
-- Node name is ':19' = 'acc1'
-- Equation name is 'acc1', location is LC6_A5, type is buried.
acc1 = DFFE( _EQ002, _LC1_A6, VCC, VCC, VCC);
_EQ002 = !acc0 & acc1 & _LC1_A4 & phaa
# acc0 & !acc1 & _LC1_A4
# !acc1 & _LC1_A4 & !phaa;
-- Node name is ':18' = 'acc2'
-- Equation name is 'acc2', location is LC8_A3, type is buried.
acc2 = DFFE( _EQ003, _LC1_A6, VCC, VCC, VCC);
_EQ003 = _LC1_A4 & _LC2_A3;
-- Node name is ':17' = 'acc3'
-- Equation name is 'acc3', location is LC5_A2, type is buried.
acc3 = DFFE( _EQ004, _LC1_A6, VCC, VCC, VCC);
_EQ004 = _LC1_A4 & _LC3_A2;
-- Node name is ':16' = 'acc4'
-- Equation name is 'acc4', location is LC7_A4, type is buried.
acc4 = DFFE( _EQ005, _LC1_A6, VCC, VCC, VCC);
_EQ005 = _LC1_A4 & _LC2_A4;
-- Node name is ':15' = 'acc5'
-- Equation name is 'acc5', location is LC1_A2, type is buried.
acc5 = DFFE( _EQ006, _LC1_A6, VCC, VCC, VCC);
_EQ006 = _LC1_A4 & _LC2_A2;
-- Node name is ':14' = 'acc6'
-- Equation name is 'acc6', location is LC6_A1, type is buried.
acc6 = DFFE( _EQ007, _LC1_A6, VCC, VCC, VCC);
_EQ007 = _LC1_A1 & _LC1_A4;
-- Node name is ':13' = 'acc7'
-- Equation name is 'acc7', location is LC3_A1, type is buried.
acc7 = DFFE( _EQ008, _LC1_A6, VCC, VCC, VCC);
_EQ008 = _LC1_A4 & _LC4_A1 & phaa
# _LC1_A4 & _LC7_A1 & !phaa;
-- Node name is 'clr_in2'
-- Equation name is 'clr_in2', type is output
clr_in2 = _LC1_A6;
-- Node name is 'pha0'
-- Equation name is 'pha0', type is output
pha0 = acc0;
-- Node name is 'pha1'
-- Equation name is 'pha1', type is output
pha1 = acc1;
-- Node name is 'pha2'
-- Equation name is 'pha2', type is output
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