phader.vhd

来自「这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity phader is
port(sysclk:in std_logic;
     a:in std_logic_vector(7 downto 0);
     b:in std_logic_vector(8 downto 0);
     --clr_in:out std_logic;
     badress:out std_logic_vector(9 downto 0));
end phader;     
     
architecture behav of phader is
signal acc:std_logic_vector(9 downto 0);
begin
process(sysclk)
begin
if(sysclk'event and sysclk='1')then 
        acc<='0'&b+a;
        badress<=acc;
            end if;
               end process ;       
end behav;