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这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）

adata3   =  _LC1_C21;

-- Node name is 'adata4~fit~in1' 
-- Equation name is 'adata4~fit~in1', location is LC1_C23, type is buried.
-- synthesized logic cell 
_LC1_C23 = LCELL( _EC3_C);

-- Node name is 'adata4' 
-- Equation name is 'adata4', type is output 
adata4   =  _LC1_C23;

-- Node name is 'adata5~fit~in1' 
-- Equation name is 'adata5~fit~in1', location is LC1_C27, type is buried.
-- synthesized logic cell 
_LC1_C27 = LCELL( _EC11_C);

-- Node name is 'adata5' 
-- Equation name is 'adata5', type is output 
adata5   =  _LC1_C27;

-- Node name is 'adata6~fit~in1' 
-- Equation name is 'adata6~fit~in1', location is LC1_C29, type is buried.
-- synthesized logic cell 
_LC1_C29 = LCELL( _EC2_C);

-- Node name is 'adata6' 
-- Equation name is 'adata6', type is output 
adata6   =  _LC1_C29;

-- Node name is 'adata7~fit~in1' 
-- Equation name is 'adata7~fit~in1', location is LC1_C30, type is buried.
-- synthesized logic cell 
_LC1_C30 = LCELL( _EC10_C);

-- Node name is 'adata7' 
-- Equation name is 'adata7', type is output 
adata7   =  _LC1_C30;

-- Node name is 'bdata0~fit~in1' 
-- Equation name is 'bdata0~fit~in1', location is LC8_A7, type is buried.
-- synthesized logic cell 
_LC8_A7  = LCELL( _EC2_A);

-- Node name is 'bdata0' 
-- Equation name is 'bdata0', type is output 
bdata0   =  _LC8_A7;

-- Node name is 'bdata1~fit~in1' 
-- Equation name is 'bdata1~fit~in1', location is LC6_B9, type is buried.
-- synthesized logic cell 
_LC6_B9  = LCELL( _EC10_A);

-- Node name is 'bdata1' 
-- Equation name is 'bdata1', type is output 
bdata1   =  _LC6_B9;

-- Node name is 'bdata2~fit~in1' 
-- Equation name is 'bdata2~fit~in1', location is LC4_C11, type is buried.
-- synthesized logic cell 
_LC4_C11 = LCELL( _EC1_A);

-- Node name is 'bdata2' 
-- Equation name is 'bdata2', type is output 
bdata2   =  _LC4_C11;

-- Node name is 'bdata3~fit~in1' 
-- Equation name is 'bdata3~fit~in1', location is LC1_D2, type is buried.
-- synthesized logic cell 
_LC1_D2  = LCELL( _EC1_D);

-- Node name is 'bdata3' 
-- Equation name is 'bdata3', type is output 
bdata3   =  _LC1_D2;

-- Node name is 'bdata4~fit~in1' 
-- Equation name is 'bdata4~fit~in1', location is LC5_D10, type is buried.
-- synthesized logic cell 
_LC5_D10 = LCELL( _EC10_D);

-- Node name is 'bdata4' 
-- Equation name is 'bdata4', type is output 
bdata4   =  _LC5_D10;

-- Node name is 'bdata5~fit~in1' 
-- Equation name is 'bdata5~fit~in1', location is LC8_D3, type is buried.
-- synthesized logic cell 
_LC8_D3  = LCELL( _EC2_D);

-- Node name is 'bdata5' 
-- Equation name is 'bdata5', type is output 
bdata5   =  _LC8_D3;

-- Node name is 'bdata6~fit~in1' 
-- Equation name is 'bdata6~fit~in1', location is LC4_E13, type is buried.
-- synthesized logic cell 
_LC4_E13 = LCELL( _EC9_D);

-- Node name is 'bdata6' 
-- Equation name is 'bdata6', type is output 
bdata6   =  _LC4_E13;

-- Node name is 'bdata7~fit~in1' 
-- Equation name is 'bdata7~fit~in1', location is LC1_F17, type is buried.
-- synthesized logic cell 
_LC1_F17 = LCELL( _EC9_A);

-- Node name is 'bdata7' 
-- Equation name is 'bdata7', type is output 
bdata7   =  _LC1_F17;

-- Node name is ':26' = 'clr_b' 
-- Equation name is 'clr_b', location is LC7_A12, type is buried.
clr_b    = DFFE( _EQ001,  _LC3_A11,  VCC,  VCC,  VCC);
  _EQ001 =  keyphin
         #  _LC1_A12
         #  keyfre;

-- Node name is '|ACHANLE:8|:29' = '|ACHANLE:8|acc0' 
-- Equation name is '_LC3_C14', type is buried 
_LC3_C14 = DFFE( _EQ002,  _LC3_A11,  VCC,  VCC,  VCC);
  _EQ002 = !clr_b & !_LC3_C14;

-- Node name is '|ACHANLE:8|:28' = '|ACHANLE:8|acc1' 
-- Equation name is '_LC4_C14', type is buried 
_LC4_C14 = DFFE( _EQ003,  _LC3_A11,  VCC,  VCC,  VCC);
  _EQ003 = !_LC2_C10 &  _LC3_C14 & !_LC4_C14
         # !_LC2_C10 & !_LC3_C14 &  _LC4_C14;

-- Node name is '|ACHANLE:8|:27' = '|ACHANLE:8|acc2' 
-- Equation name is '_LC6_C14', type is buried 
_LC6_C14 = DFFE( _EQ004,  _LC3_A11,  VCC,  VCC,  VCC);
  _EQ004 = !_LC2_C10 & !_LC3_C14 &  _LC6_C14
         # !_LC2_C10 & !_LC4_C14 &  _LC6_C14
         # !_LC2_C10 &  _LC3_C14 &  _LC4_C14 & !_LC6_C14;

-- Node name is '|ACHANLE:8|:26' = '|ACHANLE:8|acc3' 
-- Equation name is '_LC6_C1', type is buried 
_LC6_C1  = DFFE( _EQ005,  _LC3_A11,  VCC,  VCC,  VCC);
  _EQ005 = !_LC2_C10 &  _LC6_C1 & !_LC7_C14
         # !_LC2_C10 & !_LC6_C1 &  _LC7_C14;

-- Node name is '|ACHANLE:8|:25' = '|ACHANLE:8|acc4' 
-- Equation name is '_LC3_C1', type is buried 
_LC3_C1  = DFFE( _EQ006,  _LC3_A11,  VCC,  VCC,  VCC);
  _EQ006 = !_LC2_C10 &  _LC3_C1 & !_LC6_C1
         # !_LC2_C10 &  _LC3_C1 & !_LC7_C14
         # !_LC2_C10 & !_LC3_C1 &  _LC6_C1 &  _LC7_C14;

-- Node name is '|ACHANLE:8|:24' = '|ACHANLE:8|acc5' 
-- Equation name is '_LC8_C10', type is buried 
_LC8_C10 = DFFE( _EQ007,  _LC3_A11,  VCC,  VCC,  VCC);
  _EQ007 = !_LC2_C10 & !_LC3_C1 &  _LC8_C10
         # !_LC2_C10 & !_LC3_C10 &  _LC8_C10
         # !_LC2_C10 &  _LC3_C1 &  _LC3_C10 & !_LC8_C10;

-- Node name is '|ACHANLE:8|:23' = '|ACHANLE:8|acc6' 
-- Equation name is '_LC5_C10', type is buried 
_LC5_C10 = DFFE( _EQ008,  _LC3_A11,  VCC,  VCC,  VCC);
  _EQ008 = !_LC2_C10 &  _LC5_C10 & !_LC8_C10
         # !_LC2_C10 & !_LC4_C10 &  _LC5_C10
         # !_LC2_C10 &  _LC4_C10 & !_LC5_C10 &  _LC8_C10;

-- Node name is '|ACHANLE:8|:22' = '|ACHANLE:8|acc7' 
-- Equation name is '_LC5_C9', type is buried 
_LC5_C9  = DFFE( _EQ009,  _LC3_A11,  VCC,  VCC,  VCC);
  _EQ009 = !_LC2_C10 &  _LC5_C9 & !_LC7_C10
         # !_LC2_C10 & !_LC5_C9 &  _LC7_C10;

-- Node name is '|ACHANLE:8|:21' = '|ACHANLE:8|acc8' 
-- Equation name is '_LC2_C9', type is buried 
_LC2_C9  = DFFE( _EQ010,  _LC3_A11,  VCC,  VCC,  VCC);
  _EQ010 =  _LC2_C9 & !_LC2_C10 & !_LC5_C9
         #  _LC2_C9 & !_LC2_C10 & !_LC7_C10
         # !_LC2_C9 & !_LC2_C10 &  _LC5_C9 &  _LC7_C10;

-- Node name is '|ACHANLE:8|LPM_ADD_SUB:127|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C14', type is buried 
!_LC7_C14 = _LC7_C14~NOT;
_LC7_C14~NOT = LCELL( _EQ011);
  _EQ011 = !_LC6_C14
         # !_LC3_C14
         # !_LC4_C14;

-- Node name is '|ACHANLE:8|LPM_ADD_SUB:127|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C10', type is buried 
_LC3_C10 = LCELL( _EQ012);
  _EQ012 =  _LC6_C1 &  _LC7_C14;

-- Node name is '|ACHANLE:8|LPM_ADD_SUB:127|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C10', type is buried 
_LC4_C10 = LCELL( _EQ013);
  _EQ013 =  _LC3_C1 &  _LC6_C1 &  _LC7_C14;

-- Node name is '|ACHANLE:8|LPM_ADD_SUB:127|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C10', type is buried 
_LC7_C10 = LCELL( _EQ014);
  _EQ014 =  _LC4_C10 &  _LC5_C10 &  _LC8_C10;

-- Node name is '|ACHANLE:8|:3' 
-- Equation name is '_LC3_C9', type is buried 
_LC3_C9  = DFFE( _LC2_C9,  _LC3_A11,  VCC,  VCC,  VCC);

-- Node name is '|ACHANLE:8|:5' 
-- Equation name is '_LC1_C9', type is buried 
_LC1_C9  = DFFE( _LC5_C9,  _LC3_A11,  VCC,  VCC,  VCC);

-- Node name is '|ACHANLE:8|:7' 
-- Equation name is '_LC1_C15', type is buried 
_LC1_C15 = DFFE( _LC5_C10,  _LC3_A11,  VCC,  VCC,  VCC);

-- Node name is '|ACHANLE:8|:9' 
-- Equation name is '_LC1_C10', type is buried 
_LC1_C10 = DFFE( _LC8_C10,  _LC3_A11,  VCC,  VCC,  VCC);

-- Node name is '|ACHANLE:8|:11' 
-- Equation name is '_LC1_C5', type is buried 
_LC1_C5  = DFFE( _LC3_C1,  _LC3_A11,  VCC,  VCC,  VCC);

-- Node name is '|ACHANLE:8|:13' 
-- Equation name is '_LC1_C1', type is buried 
_LC1_C1  = DFFE( _LC6_C1,  _LC3_A11,  VCC,  VCC,  VCC);

-- Node name is '|ACHANLE:8|:15' 
-- Equation name is '_LC5_C14', type is buried 
_LC5_C14 = DFFE( _LC6_C14,  _LC3_A11,  VCC,  VCC,  VCC);

-- Node name is '|ACHANLE:8|:17' 
-- Equation name is '_LC2_C14', type is buried 
_LC2_C14 = DFFE( _LC4_C14,  _LC3_A11,  VCC,  VCC,  VCC);

-- Node name is '|ACHANLE:8|:19' 
-- Equation name is '_LC1_C14', type is buried 
_LC1_C14 = DFFE( _LC3_C14,  _LC3_A11,  VCC,  VCC,  VCC);

-- Node name is '|ACHANLE:8|~71~1' 
-- Equation name is '_LC4_C9', type is buried 
-- synthesized logic cell 
_LC4_C9  = LCELL( _EQ015);
  _EQ015 = !_LC5_C10
         #  _LC5_C9
         # !_LC2_C9;

-- Node name is '|ACHANLE:8|~71~2' 
-- Equation name is '_LC6_C10', type is buried 
-- synthesized logic cell 
_LC6_C10 = LCELL( _EQ016);
  _EQ016 = !_LC8_C10
         #  _LC4_C9
         #  _LC6_C1
         #  _LC3_C1;

-- Node name is '|ACHANLE:8|:81' 
-- Equation name is '_LC2_C10', type is buried 
!_LC2_C10 = _LC2_C10~NOT;