📄 top.rpt
字号:
- 1 - C 30 SOFT s r 0 1 1 0 adata7~fit~in1
- - 1 C -- MEM_SGMT 0 9 0 1 |arom:7|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 9 C -- MEM_SGMT 0 9 0 1 |arom:7|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 4 C -- MEM_SGMT 0 9 0 1 |arom:7|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 12 C -- MEM_SGMT 0 9 0 1 |arom:7|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 3 C -- MEM_SGMT 0 9 0 1 |arom:7|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 11 C -- MEM_SGMT 0 9 0 1 |arom:7|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 2 C -- MEM_SGMT 0 9 0 1 |arom:7|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 10 C -- MEM_SGMT 0 9 0 1 |arom:7|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- 4 - A 02 AND2 0 3 0 5 |BCHANLE:24|LPM_ADD_SUB:160|addcore:adder|:79
- 5 - D 16 AND2 0 2 0 1 |BCHANLE:24|LPM_ADD_SUB:160|addcore:adder|:83
- 4 - D 16 AND2 0 4 0 2 |BCHANLE:24|LPM_ADD_SUB:160|addcore:adder|:91
- 4 - D 06 AND2 0 2 0 2 |BCHANLE:24|LPM_ADD_SUB:160|addcore:adder|:95
- 7 - D 08 DFFE 0 2 0 2 |BCHANLE:24|:3
- 8 - D 08 DFFE 0 2 0 3 |BCHANLE:24|:5
- 3 - D 06 DFFE 0 2 0 2 |BCHANLE:24|:7
- 2 - D 14 DFFE 0 2 0 2 |BCHANLE:24|:9
- 2 - D 16 DFFE 0 2 0 2 |BCHANLE:24|:11
- 1 - D 16 DFFE 0 2 0 2 |BCHANLE:24|:13
- 5 - A 02 DFFE 0 2 0 2 |BCHANLE:24|:15
- 1 - A 02 DFFE 0 2 0 2 |BCHANLE:24|:17
- 3 - A 02 DFFE 0 2 0 3 |BCHANLE:24|:19
- 1 - D 06 DFFE 0 4 0 2 |BCHANLE:24|acc8 (|BCHANLE:24|:21)
- 2 - D 06 DFFE 0 3 0 3 |BCHANLE:24|acc7 (|BCHANLE:24|:22)
- 5 - D 06 DFFE 0 3 0 3 |BCHANLE:24|acc6 (|BCHANLE:24|:23)
- 7 - D 16 DFFE 0 4 0 3 |BCHANLE:24|acc5 (|BCHANLE:24|:24)
- 6 - D 16 DFFE 0 4 0 4 |BCHANLE:24|acc4 (|BCHANLE:24|:25)
- 8 - D 16 DFFE 0 3 0 5 |BCHANLE:24|acc3 (|BCHANLE:24|:26)
- 2 - A 02 DFFE 0 4 0 2 |BCHANLE:24|acc2 (|BCHANLE:24|:27)
- 6 - A 02 DFFE 0 3 0 3 |BCHANLE:24|acc1 (|BCHANLE:24|:28)
- 7 - A 02 DFFE 0 2 0 4 |BCHANLE:24|acc0 (|BCHANLE:24|:29)
- 7 - D 06 OR2 0 3 0 1 |BCHANLE:24|:81
- 3 - D 16 AND2 0 3 0 1 |BCHANLE:24|:88
- 6 - D 06 OR2 ! 0 4 0 9 |BCHANLE:24|:114
- 8 - A 07 SOFT s r 0 1 1 0 bdata0~fit~in1
- 6 - B 09 SOFT s r 0 1 1 0 bdata1~fit~in1
- 4 - C 11 SOFT s r 0 1 1 0 bdata2~fit~in1
- 1 - D 02 SOFT s r 0 1 1 0 bdata3~fit~in1
- 5 - D 10 SOFT s r 0 1 1 0 bdata4~fit~in1
- 8 - D 03 SOFT s r 0 1 1 0 bdata5~fit~in1
- 4 - E 13 SOFT s r 0 1 1 0 bdata6~fit~in1
- 1 - F 17 SOFT s r 0 1 1 0 bdata7~fit~in1
- 7 - D 07 AND2 0 2 0 4 |BFENPIN:15|LPM_ADD_SUB:63|addcore:adder|:55
- 3 - D 07 DFFE + 0 4 0 18 |BFENPIN:15|:7
- 6 - D 07 DFFE 0 4 0 2 |BFENPIN:15|acc3 (|BFENPIN:15|:9)
- 1 - D 07 DFFE 0 4 0 3 |BFENPIN:15|acc2 (|BFENPIN:15|:10)
- 2 - D 07 DFFE 0 4 0 1 |BFENPIN:15|acc1 (|BFENPIN:15|:11)
- 4 - D 07 DFFE 0 3 0 2 |BFENPIN:15|acc0 (|BFENPIN:15|:12)
- 5 - D 07 AND2 0 3 0 3 |BFENPIN:15|:30
- - 2 A -- MEM_SGMT 0 10 0 1 |brom:31|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 10 A -- MEM_SGMT 0 10 0 1 |brom:31|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 1 A -- MEM_SGMT 0 10 0 1 |brom:31|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 1 D -- MEM_SGMT 0 10 0 1 |brom:31|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 10 D -- MEM_SGMT 0 10 0 1 |brom:31|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 2 D -- MEM_SGMT 0 10 0 1 |brom:31|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 9 D -- MEM_SGMT 0 10 0 1 |brom:31|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 9 A -- MEM_SGMT 0 10 0 1 |brom:31|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- 1 - A 11 AND2 0 3 0 4 |HZ100:6|LPM_ADD_SUB:40|addcore:adder|:79
- 2 - A 03 AND2 0 4 0 3 |HZ100:6|LPM_ADD_SUB:40|addcore:adder|:91
- 5 - A 12 DFFE 0 2 0 1 |HZ100:6|:2
- 4 - A 12 DFFE 0 4 0 1 |HZ100:6|acc8 (|HZ100:6|:4)
- 3 - A 12 DFFE 0 3 0 1 |HZ100:6|acc7 (|HZ100:6|:5)
- 2 - A 12 DFFE 0 2 0 2 |HZ100:6|acc6 (|HZ100:6|:6)
- 6 - A 03 DFFE 0 4 0 1 |HZ100:6|acc5 (|HZ100:6|:7)
- 5 - A 03 DFFE 0 3 0 2 |HZ100:6|acc4 (|HZ100:6|:8)
- 4 - A 03 DFFE 0 2 0 3 |HZ100:6|acc3 (|HZ100:6|:9)
- 8 - A 11 DFFE 0 3 0 1 |HZ100:6|acc2 (|HZ100:6|:10)
- 7 - A 11 DFFE 0 2 0 2 |HZ100:6|acc1 (|HZ100:6|:11)
- 6 - A 11 DFFE 0 1 0 3 |HZ100:6|acc0 (|HZ100:6|:12)
- 5 - F 05 DFFE 2 0 0 3 |MCU:33|:12
- 1 - F 05 DFFE 2 0 0 2 |MCU:33|:14
- 7 - A 04 DFFE 2 0 0 2 |MCU:33|:16
- 8 - A 04 DFFE 2 0 0 2 |MCU:33|:18
- 1 - D 18 DFFE 2 0 0 2 |MCU:33|:20
- 7 - D 15 DFFE 2 0 0 2 |MCU:33|:22
- 6 - D 15 DFFE 2 0 0 2 |MCU:33|:24
- 3 - A 05 DFFE 2 0 0 3 |MCU:33|:26
- 2 - D 15 DFFE 2 0 0 1 |MCU:33|:28
- 7 - D 11 DFFE 2 0 0 1 |MCU:33|:30
- 2 - D 09 DFFE 2 0 0 1 |MCU:33|:32
- 1 - B 10 DFFE 2 0 0 1 |MCU:33|:34
- 7 - A 01 OR2 0 4 0 2 |PHADER:17|LPM_ADD_SUB:123|addcore:adder|pcarry1
- 8 - A 01 OR2 0 3 0 2 |PHADER:17|LPM_ADD_SUB:123|addcore:adder|pcarry2
- 1 - A 06 OR2 0 3 0 2 |PHADER:17|LPM_ADD_SUB:123|addcore:adder|pcarry3
- 4 - A 04 OR2 0 3 0 2 |PHADER:17|LPM_ADD_SUB:123|addcore:adder|pcarry4
- 2 - A 04 OR2 0 3 0 2 |PHADER:17|LPM_ADD_SUB:123|addcore:adder|pcarry5
- 4 - D 08 OR2 0 3 0 3 |PHADER:17|LPM_ADD_SUB:123|addcore:adder|pcarry6
- 2 - D 17 DFFE 0 2 0 8 |PHADER:17|:19
- 1 - D 08 DFFE 0 2 0 8 |PHADER:17|:21
- 2 - D 08 DFFE 0 2 0 8 |PHADER:17|:23
- 2 - D 13 DFFE 0 2 0 8 |PHADER:17|:25
- 3 - A 04 DFFE 0 2 0 8 |PHADER:17|:27
- 1 - A 04 DFFE 0 2 0 8 |PHADER:17|:29
- 1 - A 03 DFFE 0 2 0 8 |PHADER:17|:31
- 1 - A 01 DFFE 0 2 0 8 |PHADER:17|:33
- 5 - A 01 DFFE 0 2 0 8 |PHADER:17|:35
- 3 - A 01 DFFE 0 2 0 8 |PHADER:17|:37
- 3 - D 08 DFFE 0 5 0 1 |PHADER:17|acc9 (|PHADER:17|:39)
- 6 - D 08 DFFE 0 5 0 1 |PHADER:17|acc8 (|PHADER:17|:40)
- 5 - D 08 DFFE 0 4 0 1 |PHADER:17|acc7 (|PHADER:17|:41)
- 1 - D 13 DFFE 0 4 0 1 |PHADER:17|acc6 (|PHADER:17|:42)
- 6 - A 04 DFFE 0 4 0 1 |PHADER:17|acc5 (|PHADER:17|:43)
- 5 - A 04 DFFE 0 4 0 1 |PHADER:17|acc4 (|PHADER:17|:44)
- 3 - A 03 DFFE 0 4 0 1 |PHADER:17|acc3 (|PHADER:17|:45)
- 6 - A 01 DFFE 0 4 0 1 |PHADER:17|acc2 (|PHADER:17|:46)
- 4 - A 01 DFFE 0 5 0 1 |PHADER:17|acc1 (|PHADER:17|:47)
- 2 - A 01 DFFE 0 3 0 1 |PHADER:17|acc0 (|PHADER:17|:48)
- 3 - A 11 DFFE + 0 1 0 54 |SYSCLOCK:29|:2
- 4 - A 11 DFFE + 0 2 0 1 |SYSCLOCK:29|acc2 (|SYSCLOCK:29|:4)
- 2 - A 11 DFFE + 0 1 0 1 |SYSCLOCK:29|acc1 (|SYSCLOCK:29|:5)
- 5 - A 11 DFFE + 0 0 0 2 |SYSCLOCK:29|acc0 (|SYSCLOCK:29|:6)
- 1 - A 12 DFFE 1 1 0 1 :11
- 7 - A 12 DFFE 2 2 0 3 clr_b (:26)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\lishanew\top.rpt
top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 12/144( 8%) 23/ 72( 31%) 0/ 72( 0%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
B: 2/144( 1%) 2/ 72( 2%) 0/ 72( 0%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
C: 19/144( 13%) 10/ 72( 13%) 0/ 72( 0%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
D: 16/144( 11%) 24/ 72( 33%) 0/ 72( 0%) 3/16( 18%) 3/16( 18%) 0/16( 0%)
E: 3/144( 2%) 1/ 72( 1%) 0/ 72( 0%) 2/16( 12%) 1/16( 6%) 0/16( 0%)
F: 3/144( 2%) 2/ 72( 2%) 0/ 72( 0%) 2/16( 12%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\lishanew\top.rpt
top
** CLOCK SIGNALS **
Type Fan-out Name
DFF 54 |SYSCLOCK:29|:2
INPUT 21 clk
DFF 18 |BFENPIN:15|:7
INPUT 9 keyphin
INPUT 5 keyfre
DFF 1 |HZ100:6|:2
Device-Specific Information: f:\lishanew\top.rpt
top
** EQUATIONS **
clk : INPUT;
ddin0 : INPUT;
ddin1 : INPUT;
ddin2 : INPUT;
ddin3 : INPUT;
ddin4 : INPUT;
ddin5 : INPUT;
ddin6 : INPUT;
ddin7 : INPUT;
keyclr : INPUT;
keyfre : INPUT;
keyphin : INPUT;
-- Node name is 'adata0~fit~in1'
-- Equation name is 'adata0~fit~in1', location is LC1_C7, type is buried.
-- synthesized logic cell
_LC1_C7 = LCELL( _EC1_C);
-- Node name is 'adata0'
-- Equation name is 'adata0', type is output
adata0 = _LC1_C7;
-- Node name is 'adata1~fit~in1'
-- Equation name is 'adata1~fit~in1', location is LC1_C13, type is buried.
-- synthesized logic cell
_LC1_C13 = LCELL( _EC9_C);
-- Node name is 'adata1'
-- Equation name is 'adata1', type is output
adata1 = _LC1_C13;
-- Node name is 'adata2~fit~in1'
-- Equation name is 'adata2~fit~in1', location is LC1_C17, type is buried.
-- synthesized logic cell
_LC1_C17 = LCELL( _EC4_C);
-- Node name is 'adata2'
-- Equation name is 'adata2', type is output
adata2 = _LC1_C17;
-- Node name is 'adata3~fit~in1'
-- Equation name is 'adata3~fit~in1', location is LC1_C21, type is buried.
-- synthesized logic cell
_LC1_C21 = LCELL( _EC12_C);
-- Node name is 'adata3'
-- Equation name is 'adata3', type is output
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -