📄 top.rpt
字号:
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R V R G V G G G G G R R V R R R R G R R R R V R
E E E N E E E E C E E E E C E N C N N N N N E E C E E E E N E E E E C E
S S S D S S S S C S S S S C S D C D D D D D S S C S S S S D S S S S C S
E E E E E E E I E E E E I E I E E I E E E E E E E E I E
R R R R R R R O R R R R N R N R R O R R R R R R R R O R
V V V V V V V V V V V T V T V V V V V V V V V V V
E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: f:\lishanew\top.rpt
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** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 7/22( 31%)
A2 7/ 8( 87%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 2/22( 9%)
A3 6/ 8( 75%) 1/ 8( 12%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
A4 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 7/22( 31%)
A5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
A6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
A7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
A11 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 0/22( 0%)
A12 6/ 8( 75%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 5/22( 22%)
B9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
B10 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
C1 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
C5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
C7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C9 5/ 8( 62%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
C10 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 6/22( 27%)
C11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C14 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
C15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
C17 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C23 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C27 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C29 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
C30 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
D2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
D3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
D6 7/ 8( 87%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 5/22( 22%)
D7 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 5/22( 22%)
D8 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 8/22( 36%)
D9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
D10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
D11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
D13 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
D14 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
D15 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 5/22( 22%)
D16 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
D17 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
D18 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
E13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
F5 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 1/2 0/2 3/22( 13%)
F17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A37 4/16( 25%) 3/16( 18%) 1/16( 6%) 1/2 2/6 10/88( 11%)
C37 8/16( 50%) 0/16( 0%) 8/16( 50%) 1/2 2/6 9/88( 10%)
D37 4/16( 25%) 1/16( 6%) 3/16( 18%) 1/2 2/6 10/88( 11%)
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 27/96 ( 28%)
Total logic cells used: 129/1728 ( 7%)
Total embedded cells used: 16/96 ( 16%)
Total EABs used: 3/6 ( 50%)
Average fan-in: 2.14/4 ( 53%)
Total fan-in: 277/6912 ( 4%)
Total input pins required: 12
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 129
Total flipflops required: 89
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Logic cells inserted for fitting: 16
Synthesized logic cells: 18/1728 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 8 7 6 8 1 1 1 0 0 0 8 6 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46/4
B: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2/0
C: 3 0 0 0 1 0 1 0 5 8 1 0 1 7 1 0 1 0 8 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 34/8
D: 0 1 1 0 0 7 7 8 1 1 1 0 2 1 3 8 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43/4
E: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
F: 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3/0
Total: 11 8 7 8 4 8 9 8 7 10 10 6 4 8 4 8 3 1 16 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 129/16
Device-Specific Information: f:\lishanew\top.rpt
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** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - - -- INPUT G ^ 0 0 0 0 clk
17 - - C -- INPUT ^ 0 0 0 2 ddin0
19 - - D -- INPUT ^ 0 0 0 2 ddin1
21 - - D -- INPUT ^ 0 0 0 2 ddin2
23 - - D -- INPUT ^ 0 0 0 2 ddin3
26 - - E -- INPUT ^ 0 0 0 1 ddin4
28 - - E -- INPUT ^ 0 0 0 1 ddin5
30 - - F -- INPUT ^ 0 0 0 1 ddin6
32 - - F -- INPUT ^ 0 0 0 1 ddin7
118 - - - 09 INPUT ^ 0 0 0 1 keyclr
10 - - B -- INPUT ^ 0 0 0 5 keyfre
8 - - A -- INPUT ^ 0 0 0 9 keyphin
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\lishanew\top.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
117 - - - 08 OUTPUT 0 1 0 0 adata0
119 - - - 13 OUTPUT 0 1 0 0 adata1
121 - - - 17 OUTPUT 0 1 0 0 adata2
130 - - - 22 OUTPUT 0 1 0 0 adata3
131 - - - 23 OUTPUT 0 1 0 0 adata4
133 - - - 28 OUTPUT 0 1 0 0 adata5
135 - - - 29 OUTPUT 0 1 0 0 adata6
137 - - - 30 OUTPUT 0 1 0 0 adata7
100 - - A -- OUTPUT 0 1 0 0 bdata0
98 - - B -- OUTPUT 0 1 0 0 bdata1
96 - - C -- OUTPUT 0 1 0 0 bdata2
92 - - D -- OUTPUT 0 1 0 0 bdata3
90 - - D -- OUTPUT 0 1 0 0 bdata4
88 - - D -- OUTPUT 0 1 0 0 bdata5
86 - - E -- OUTPUT 0 1 0 0 bdata6
82 - - F -- OUTPUT 0 1 0 0 bdata7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\lishanew\top.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - C 14 OR2 ! 0 3 0 5 |ACHANLE:8|LPM_ADD_SUB:127|addcore:adder|:79
- 3 - C 10 AND2 0 2 0 1 |ACHANLE:8|LPM_ADD_SUB:127|addcore:adder|:83
- 4 - C 10 AND2 0 3 0 2 |ACHANLE:8|LPM_ADD_SUB:127|addcore:adder|:87
- 7 - C 10 AND2 0 3 0 2 |ACHANLE:8|LPM_ADD_SUB:127|addcore:adder|:95
- 3 - C 09 DFFE 0 2 0 8 |ACHANLE:8|:3
- 1 - C 09 DFFE 0 2 0 8 |ACHANLE:8|:5
- 1 - C 15 DFFE 0 2 0 8 |ACHANLE:8|:7
- 1 - C 10 DFFE 0 2 0 8 |ACHANLE:8|:9
- 1 - C 05 DFFE 0 2 0 8 |ACHANLE:8|:11
- 1 - C 01 DFFE 0 2 0 8 |ACHANLE:8|:13
- 5 - C 14 DFFE 0 2 0 8 |ACHANLE:8|:15
- 2 - C 14 DFFE 0 2 0 8 |ACHANLE:8|:17
- 1 - C 14 DFFE 0 2 0 8 |ACHANLE:8|:19
- 2 - C 09 DFFE 0 4 0 2 |ACHANLE:8|acc8 (|ACHANLE:8|:21)
- 5 - C 09 DFFE 0 3 0 3 |ACHANLE:8|acc7 (|ACHANLE:8|:22)
- 5 - C 10 DFFE 0 4 0 3 |ACHANLE:8|acc6 (|ACHANLE:8|:23)
- 8 - C 10 DFFE 0 4 0 4 |ACHANLE:8|acc5 (|ACHANLE:8|:24)
- 3 - C 01 DFFE 0 4 0 4 |ACHANLE:8|acc4 (|ACHANLE:8|:25)
- 6 - C 01 DFFE 0 3 0 5 |ACHANLE:8|acc3 (|ACHANLE:8|:26)
- 6 - C 14 DFFE 0 4 0 2 |ACHANLE:8|acc2 (|ACHANLE:8|:27)
- 4 - C 14 DFFE 0 3 0 3 |ACHANLE:8|acc1 (|ACHANLE:8|:28)
- 3 - C 14 DFFE 0 2 0 4 |ACHANLE:8|acc0 (|ACHANLE:8|:29)
- 4 - C 09 OR2 s 0 3 0 1 |ACHANLE:8|~71~1
- 6 - C 10 OR2 s 0 4 0 1 |ACHANLE:8|~71~2
- 2 - C 10 OR2 ! 0 3 0 8 |ACHANLE:8|:81
- 1 - C 07 SOFT s r 0 1 1 0 adata0~fit~in1
- 1 - C 13 SOFT s r 0 1 1 0 adata1~fit~in1
- 1 - C 17 SOFT s r 0 1 1 0 adata2~fit~in1
- 1 - C 21 SOFT s r 0 1 1 0 adata3~fit~in1
- 1 - C 23 SOFT s r 0 1 1 0 adata4~fit~in1
- 1 - C 27 SOFT s r 0 1 1 0 adata5~fit~in1
- 1 - C 29 SOFT s r 0 1 1 0 adata6~fit~in1
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