bfreyuz.vhd

来自「这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器」· VHDL 代码 · 共 19 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bfreyuz is
port(bfr_clk:in std_logic;
     rate:out std_logic_vector(3 downto 0));
end bfreyuz;
architecture behav of bfreyuz is
signal acc:std_logic_vector(3 downto 0);
begin
process(bfr_clk)
begin
if(bfr_clk'event and bfr_clk='1')then
  acc<=acc+1;
  rate<=acc;
     end if;
end process;
end behav;