achanle.vhd

来自「这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity achanle is
port(sysclk,clr_a:in std_logic;
     aadress:out std_logic_vector(8 downto 0));
end achanle;
architecture behav of achanle is
signal acc:std_logic_vector(8 downto 0);
begin
process(sysclk)
begin
if(sysclk'event and sysclk='1')then
   if(clr_a='1'or acc=359)then acc<=(others=>'0');
     else acc<=acc+1;
       end if;
          end if;
              end process;
process(sysclk)
begin
if(sysclk'event and sysclk='1')then
   aadress<=acc;
   end if;
   end process;
   end behav;