📄 test2.rpt
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B1 7/ 8( 87%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 9/22( 40%)
B3 6/ 8( 75%) 3/ 8( 37%) 0/ 8( 0%) 2/2 0/2 6/22( 27%)
B4 3/ 8( 37%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
B5 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
B10 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
B14 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 2/2 0/2 3/22( 13%)
B15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
B16 5/ 8( 62%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 5/22( 22%)
B17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
C2 7/ 8( 87%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 6/22( 27%)
C6 3/ 8( 37%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
C8 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
D13 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
D15 7/ 8( 87%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A37 8/16( 50%) 5/16( 31%) 3/16( 18%) 1/2 2/6 9/88( 10%)
Total dedicated input pins used: 5/6 ( 83%)
Total I/O pins used: 8/96 ( 8%)
Total logic cells used: 114/1728 ( 6%)
Total embedded cells used: 8/96 ( 8%)
Total EABs used: 1/6 ( 16%)
Average fan-in: 2.70/4 ( 67%)
Total fan-in: 308/6912 ( 4%)
Total input pins required: 5
Total input I/O cell registers required: 0
Total output pins required: 8
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 114
Total flipflops required: 72
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 4/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 1 0 1 1 1 1 6 1 1 1 1 1 1 3 7 7 6 6 8 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48/8
B: 7 0 6 3 7 0 0 0 0 1 0 1 0 7 1 5 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40/0
C: 0 7 0 0 0 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 7 7 4 8 4 6 2 1 2 1 2 9 10 15 12 7 7 8 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 114/8
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\test2.rpt
test2
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - - -- INPUT ^ 0 0 0 1 bfre
56 - - - -- INPUT ^ 0 0 0 1 clr
124 - - - -- INPUT ^ 0 0 0 1 keypha
54 - - - -- INPUT ^ 0 0 0 1 keyphb
55 - - - -- INPUT G ^ 0 0 0 0 sysclk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\test2.rpt
test2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
101 - - A -- OUTPUT 0 1 0 0 data0
20 - - D -- OUTPUT 0 1 0 0 data1
14 - - C -- OUTPUT 0 1 0 0 data2
95 - - C -- OUTPUT 0 1 0 0 data3
8 - - A -- OUTPUT 0 1 0 0 data4
12 - - C -- OUTPUT 0 1 0 0 data5
10 - - B -- OUTPUT 0 1 0 0 data6
100 - - A -- OUTPUT 0 1 0 0 data7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\test2.rpt
test2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 07 OR2 ! 0 3 0 5 |ACHANLE:7|LPM_ADD_SUB:127|addcore:adder|:79
- 1 - A 19 AND2 0 2 0 1 |ACHANLE:7|LPM_ADD_SUB:127|addcore:adder|:83
- 2 - A 10 AND2 0 3 0 2 |ACHANLE:7|LPM_ADD_SUB:127|addcore:adder|:87
- 6 - A 16 AND2 0 3 0 2 |ACHANLE:7|LPM_ADD_SUB:127|addcore:adder|:95
- 3 - A 16 DFFE 0 2 0 1 |ACHANLE:7|:3
- 6 - A 15 DFFE 0 2 0 2 |ACHANLE:7|:5
- 3 - A 17 DFFE 0 2 0 2 |ACHANLE:7|:7
- 5 - A 17 DFFE 0 2 0 2 |ACHANLE:7|:9
- 2 - A 14 DFFE 0 2 0 2 |ACHANLE:7|:11
- 1 - B 03 DFFE 0 2 0 2 |ACHANLE:7|:13
- 2 - B 03 DFFE 0 2 0 2 |ACHANLE:7|:15
- 3 - A 07 DFFE 0 2 0 2 |ACHANLE:7|:17
- 2 - A 07 DFFE 0 2 0 3 |ACHANLE:7|:19
- 7 - A 16 DFFE 0 4 0 2 |ACHANLE:7|acc8 (|ACHANLE:7|:21)
- 1 - A 16 DFFE 0 3 0 3 |ACHANLE:7|acc7 (|ACHANLE:7|:22)
- 1 - A 12 DFFE 0 4 0 3 |ACHANLE:7|acc6 (|ACHANLE:7|:23)
- 8 - A 06 DFFE 0 4 0 4 |ACHANLE:7|acc5 (|ACHANLE:7|:24)
- 1 - A 01 DFFE 0 4 0 4 |ACHANLE:7|acc4 (|ACHANLE:7|:25)
- 2 - A 09 DFFE 0 3 0 5 |ACHANLE:7|acc3 (|ACHANLE:7|:26)
- 4 - A 07 DFFE 0 4 0 2 |ACHANLE:7|acc2 (|ACHANLE:7|:27)
- 6 - A 07 DFFE 0 3 0 3 |ACHANLE:7|acc1 (|ACHANLE:7|:28)
- 1 - A 07 DFFE 0 2 0 4 |ACHANLE:7|acc0 (|ACHANLE:7|:29)
- 5 - A 16 OR2 s 0 3 0 1 |ACHANLE:7|~71~1
- 4 - A 16 OR2 s 0 4 0 1 |ACHANLE:7|~71~2
- 2 - A 16 OR2 ! 0 3 0 8 |ACHANLE:7|:81
- - 2 A -- MEM_SGMT 0 9 1 0 |arom:8|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 12 A -- MEM_SGMT 0 9 1 0 |arom:8|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 4 A -- MEM_SGMT 0 9 1 0 |arom:8|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 11 A -- MEM_SGMT 0 9 1 0 |arom:8|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 1 A -- MEM_SGMT 0 9 1 0 |arom:8|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 10 A -- MEM_SGMT 0 9 1 0 |arom:8|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 3 A -- MEM_SGMT 0 9 1 0 |arom:8|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 9 A -- MEM_SGMT 0 9 1 0 |arom:8|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- 1 - B 16 AND2 0 4 0 6 |BFENPIN:6|LPM_ADD_SUB:83|addcore:adder|:67
- 2 - B 16 OR2 0 3 0 1 |BFENPIN:6|LPM_ADD_SUB:83|addcore:adder|:76
- 3 - B 16 OR2 0 4 0 1 |BFENPIN:6|LPM_ADD_SUB:83|addcore:adder|:77
- 1 - B 10 DFFE + 0 1 0 18 |BFENPIN:6|:6
- 2 - B 17 DFFE + 0 1 0 6 |BFENPIN:6|acc4 (|BFENPIN:6|:8)
- 4 - B 16 DFFE + 0 4 0 2 |BFENPIN:6|acc3 (|BFENPIN:6|:9)
- 5 - B 16 DFFE + 0 4 0 3 |BFENPIN:6|acc2 (|BFENPIN:6|:10)
- 1 - B 14 DFFE + 0 4 0 4 |BFENPIN:6|acc1 (|BFENPIN:6|:11)
- 3 - B 14 DFFE + 0 3 0 4 |BFENPIN:6|acc0 (|BFENPIN:6|:12)
- 4 - B 14 OR2 0 4 0 1 |BFENPIN:6|:123
- 2 - B 14 DFFE 0 4 0 1 |BFREYUZ:1|acc3 (|BFREYUZ:1|:6)
- 6 - B 14 DFFE 0 3 0 2 |BFREYUZ:1|acc2 (|BFREYUZ:1|:7)
- 5 - B 14 DFFE 0 2 0 3 |BFREYUZ:1|acc1 (|BFREYUZ:1|:8)
- 7 - B 14 DFFE 0 1 0 4 |BFREYUZ:1|acc0 (|BFREYUZ:1|:9)
- 7 - D 15 AND2 0 3 0 3 |HZ100:3|LPM_ADD_SUB:48|addcore:adder|:87
- 1 - D 15 AND2 0 3 0 4 |HZ100:3|LPM_ADD_SUB:48|addcore:adder|:95
- 6 - D 13 AND2 0 4 0 3 |HZ100:3|LPM_ADD_SUB:48|addcore:adder|:107
- 3 - D 13 DFFE + 0 1 0 4 |HZ100:3|:2
- 7 - D 13 DFFE + 0 3 0 1 |HZ100:3|acc10 (|HZ100:3|:4)
- 8 - D 13 DFFE + 0 2 0 1 |HZ100:3|acc9 (|HZ100:3|:5)
- 5 - D 13 DFFE + 0 1 0 2 |HZ100:3|acc8 (|HZ100:3|:6)
- 4 - D 13 DFFE + 0 3 0 1 |HZ100:3|acc7 (|HZ100:3|:7)
- 1 - D 13 DFFE + 0 2 0 2 |HZ100:3|acc6 (|HZ100:3|:8)
- 2 - D 13 DFFE + 0 1 0 3 |HZ100:3|acc5 (|HZ100:3|:9)
- 2 - D 15 DFFE + 0 2 0 1 |HZ100:3|acc4 (|HZ100:3|:10)
- 3 - D 15 DFFE + 0 1 0 2 |HZ100:3|acc3 (|HZ100:3|:11)
- 4 - D 15 DFFE + 0 2 0 1 |HZ100:3|acc2 (|HZ100:3|:12)
- 5 - D 15 DFFE + 0 1 0 2 |HZ100:3|acc1 (|HZ100:3|:13)
- 6 - D 15 DFFE + 0 0 0 3 |HZ100:3|acc0 (|HZ100:3|:14)
- 2 - A 11 OR2 0 4 0 2 |PHADER:12|LPM_ADD_SUB:102|addcore:adder|pcarry1
- 5 - B 03 OR2 0 3 0 2 |PHADER:12|LPM_ADD_SUB:102|addcore:adder|pcarry2
- 6 - B 03 OR2 0 3 0 2 |PHADER:12|LPM_ADD_SUB:102|addcore:adder|pcarry3
- 1 - A 14 OR2 0 3 0 2 |PHADER:12|LPM_ADD_SUB:102|addcore:adder|pcarry4
- 6 - A 17 OR2 0 3 0 2 |PHADER:12|LPM_ADD_SUB:102|addcore:adder|pcarry5
- 4 - A 17 OR2 0 3 0 2 |PHADER:12|LPM_ADD_SUB:102|addcore:adder|pcarry6
- 1 - A 20 OR2 s 0 2 0 1 |PHADER:12|LPM_ADD_SUB:102|addcore:adder|~122~1
- 1 - A 15 DFFE + 0 1 0 8 |PHADER:12|:21
- 2 - A 15 DFFE + 0 1 0 8 |PHADER:12|:23
- 1 - A 08 DFFE + 0 1 0 8 |PHADER:12|:25
- 1 - A 04 DFFE + 0 1 0 8 |PHADER:12|:27
- 3 - A 03 DFFE + 0 1 0 8 |PHADER:12|:29
- 1 - A 13 DFFE + 0 1 0 8 |PHADER:12|:31
- 4 - A 05 DFFE + 0 1 0 8 |PHADER:12|:33
- 2 - A 18 DFFE + 0 1 0 8 |PHADER:12|:35
- 1 - A 18 DFFE + 0 1 0 8 |PHADER:12|:37
- 5 - A 15 DFFE + 0 4 0 2 |PHADER:12|acc8 (|PHADER:12|:39)
- 4 - A 15 DFFE + 0 3 0 2 |PHADER:12|acc7 (|PHADER:12|:40)
- 1 - A 17 DFFE + 0 3 0 2 |PHADER:12|acc6 (|PHADER:12|:41)
- 2 - A 17 DFFE + 0 3 0 2 |PHADER:12|acc5 (|PHADER:12|:42)
- 5 - A 14 DFFE + 0 3 0 2 |PHADER:12|acc4 (|PHADER:12|:43)
- 4 - B 03 DFFE + 0 3 0 2 |PHADER:12|acc3 (|PHADER:12|:44)
- 3 - B 03 DFFE + 0 3 0 2 |PHADER:12|acc2 (|PHADER:12|:45)
- 6 - A 18 DFFE + 0 4 0 2 |PHADER:12|acc1 (|PHADER:12|:46)
- 5 - A 18 DFFE + 0 2 0 2 |PHADER:12|acc0 (|PHADER:12|:47)
- 3 - A 15 OR2 ! 0 4 0 1 |PHADER:12|:303
- 3 - A 18 OR2 ! 0 3 0 1 |PHADER:12|:318
- 4 - A 18 AND2 ! 0 3 0 1 |PHADER:12|:331
- 1 - C 02 AND2 0 4 0 2 |PHYUZ:13|LPM_ADD_SUB:160|addcore:adder|:83
- 5 - B 05 AND2 0 2 0 3 |PHYUZ:13|LPM_ADD_SUB:160|addcore:adder|:87
- 3 - B 05 AND2 0 3 0 2 |PHYUZ:13|LPM_ADD_SUB:160|addcore:adder|:95
- 4 - C 02 OR2 0 4 0 1 |PHYUZ:13|LPM_ADD_SUB:160|addcore:adder|:109
- 6 - B 05 OR2 0 3 0 1 |PHYUZ:13|LPM_ADD_SUB:160|addcore:adder|:112
- 6 - C 02 OR2 0 3 0 1 |PHYUZ:13|LPM_ADD_SUB:206|addcore:adder|pcarry3
- 1 - B 15 OR2 0 4 0 3 |PHYUZ:13|LPM_ADD_SUB:206|addcore:adder|:87
- 7 - B 01 AND2 0 3 0 2 |PHYUZ:13|LPM_ADD_SUB:206|addcore:adder|:95
- 7 - C 02 OR2 0 3 0 1 |PHYUZ:13|LPM_ADD_SUB:206|addcore:adder|:109
- 7 - B 05 OR2 0 3 0 1 |PHYUZ:13|LPM_ADD_SUB:206|addcore:adder|:112
- 1 - B 01 DFFE 0 5 0 2 |PHYUZ:13|acc8 (|PHYUZ:13|:14)
- 4 - B 01 DFFE 0 3 0 5 |PHYUZ:13|acc7 (|PHYUZ:13|:15)
- 1 - B 05 DFFE 0 5 0 7 |PHYUZ:13|acc6 (|PHYUZ:13|:16)
- 4 - B 05 DFFE 0 3 0 8 |PHYUZ:13|acc5 (|PHYUZ:13|:17)
- 3 - C 02 DFFE 0 3 0 6 |PHYUZ:13|acc4 (|PHYUZ:13|:18)
- 5 - C 02 DFFE 0 5 0 8 |PHYUZ:13|acc3 (|PHYUZ:13|:19)
- 2 - C 06 DFFE 0 3 0 9 |PHYUZ:13|acc2 (|PHYUZ:13|:20)
- 1 - C 08 DFFE 0 4 0 8 |PHYUZ:13|acc1 (|PHYUZ:13|:21)
- 3 - C 06 DFFE 0 3 0 7 |PHYUZ:13|acc0 (|PHYUZ:13|:22)
- 2 - B 01 OR2 0 4 0 9 |PHYUZ:13|:73
- 6 - B 01 OR2 0 4 0 1 |PHYUZ:13|:86
- 5 - B 01 AND2 s 0 2 0 1 |PHYUZ:13|~242~1
- 3 - B 01 OR2 0 4 0 1 |PHYUZ:13|:246
- 2 - B 05 OR2 0 4 0 1 |PHYUZ:13|:264
- 2 - C 02 OR2 0 4 0 1 |PHYUZ:13|:273
- 1 - C 06 OR2 0 4 0 1 |PHYUZ:13|:291
- 1 - B 04 OR2 0 2 0 10 |PHYUZ:13|:402
- 2 - B 18 DFFE 1 1 0 4 :4
- 1 - B 12 DFFE 1 1 0 1 clr_clr (:9)
- 7 - A 15 DFFE + 0 4 0 2 bclr (:18)
- 2 - B 04 DFFE 1 1 0 10 :19
- 3 - B 04 DFFE 1 1 0 1 :21
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