📄 hz100.rpt
字号:
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 02 AND2 0 3 0 4 |LPM_ADD_SUB:40|addcore:adder|:79
- 1 - A 02 AND2 0 4 0 3 |LPM_ADD_SUB:40|addcore:adder|:91
- 6 - A 01 DFFE + 0 1 1 0 :2
- 3 - A 01 DFFE + 0 3 0 1 acc8 (:4)
- 2 - A 01 DFFE + 0 2 0 1 acc7 (:5)
- 1 - A 01 DFFE + 0 1 0 2 acc6 (:6)
- 6 - A 02 DFFE + 0 3 0 1 acc5 (:7)
- 5 - A 02 DFFE + 0 2 0 2 acc4 (:8)
- 4 - A 02 DFFE + 0 1 0 3 acc3 (:9)
- 3 - A 02 DFFE + 0 2 0 1 acc2 (:10)
- 2 - A 02 DFFE + 0 1 0 2 acc1 (:11)
- 8 - A 02 DFFE + 0 0 0 3 acc0 (:12)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\hz100.rpt
hz100
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\hz100.rpt
hz100
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 sysclk
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\hz100.rpt
hz100
** EQUATIONS **
sysclk : INPUT;
-- Node name is ':12' = 'acc0'
-- Equation name is 'acc0', location is LC8_A2, type is buried.
acc0 = DFFE(!acc0, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is ':11' = 'acc1'
-- Equation name is 'acc1', location is LC2_A2, type is buried.
acc1 = DFFE( _EQ001, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ001 = acc0 & !acc1
# !acc0 & acc1;
-- Node name is ':10' = 'acc2'
-- Equation name is 'acc2', location is LC3_A2, type is buried.
acc2 = DFFE( _EQ002, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ002 = !acc0 & acc2
# !acc1 & acc2
# acc0 & acc1 & !acc2;
-- Node name is ':9' = 'acc3'
-- Equation name is 'acc3', location is LC4_A2, type is buried.
acc3 = DFFE( _EQ003, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ003 = acc3 & !_LC7_A2
# !acc3 & _LC7_A2;
-- Node name is ':8' = 'acc4'
-- Equation name is 'acc4', location is LC5_A2, type is buried.
acc4 = DFFE( _EQ004, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ004 = !acc3 & acc4
# acc4 & !_LC7_A2
# acc3 & !acc4 & _LC7_A2;
-- Node name is ':7' = 'acc5'
-- Equation name is 'acc5', location is LC6_A2, type is buried.
acc5 = DFFE( _EQ005, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ005 = !acc3 & acc5
# acc5 & !_LC7_A2
# !acc4 & acc5
# acc3 & acc4 & !acc5 & _LC7_A2;
-- Node name is ':6' = 'acc6'
-- Equation name is 'acc6', location is LC1_A1, type is buried.
acc6 = DFFE( _EQ006, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ006 = acc6 & !_LC1_A2
# !acc6 & _LC1_A2;
-- Node name is ':5' = 'acc7'
-- Equation name is 'acc7', location is LC2_A1, type is buried.
acc7 = DFFE( _EQ007, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ007 = !acc6 & acc7
# acc7 & !_LC1_A2
# acc6 & !acc7 & _LC1_A2;
-- Node name is ':4' = 'acc8'
-- Equation name is 'acc8', location is LC3_A1, type is buried.
acc8 = DFFE( _EQ008, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ008 = !acc6 & acc8
# acc8 & !_LC1_A2
# !acc7 & acc8
# acc6 & acc7 & !acc8 & _LC1_A2;
-- Node name is 'clk_hu'
-- Equation name is 'clk_hu', type is output
clk_hu = _LC6_A1;
-- Node name is '|LPM_ADD_SUB:40|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A2', type is buried
_LC7_A2 = LCELL( _EQ009);
_EQ009 = acc0 & acc1 & acc2;
-- Node name is '|LPM_ADD_SUB:40|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = LCELL( _EQ010);
_EQ010 = acc3 & acc4 & acc5 & _LC7_A2;
-- Node name is ':2'
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = DFFE( acc8, GLOBAL( sysclk), VCC, VCC, VCC);
Project Information e:\mydesign\altera\maxplus\lisha\hz100.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = off
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 34,449K
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