bfenpin.vhd

来自「这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bfenpin is
port(sysclk,clk:in std_logic;
      rate: in std_logic_vector(3 downto 0);
      bchclk:out std_logic);
end bfenpin;
architecture behav of bfenpin is
signal acc:std_logic_vector(3 downto 0);
begin
process(sysclk)
begin      
if(sysclk'event and sysclk='1')then
  if(acc="1111")then acc<=rate;
     else acc<=acc+1; 
       end if;   
 end if;
 end process;
 process(clk)
 begin
 if(clk'event and clk='1')then
    bchclk<=acc(3)and acc(2) and acc(1)and acc(0) and sysclk;
      end if;
 end process;     
 end behav;