bfenpin.fit

这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 05/07/2005 17:29:25      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "bfenpin"
BEGIN

    DEVICE = "EP1K30TC144-3";

    "clk"                          : INPUT_PIN  = 125    ;
    "rate0"                        : INPUT_PIN  = 124    ;
    "rate1"                        : INPUT_PIN  = 54     ;
    "rate2"                        : INPUT_PIN  = 56     ;
    "rate3"                        : INPUT_PIN  = 126    ;
    "sysclk"                       : INPUT_PIN  = 55     ;
    "bchclk"                       : OUTPUT_PIN = 102    ;
    "|LPM_ADD_SUB:63|addcore:adder|:55" : LOCATION   = LC6_A1 ;
    ":7"                           : LOCATION   = LC1_A1 ;
    ":9"                           : LOCATION   = LC5_A1 ;  -- acc3
    ":10"                          : LOCATION   = LC4_A1 ;  -- acc2
    ":11"                          : LOCATION   = LC3_A1 ;  -- acc1
    ":12"                          : LOCATION   = LC2_A1 ;  -- acc0
    ":30"                          : LOCATION   = LC7_A1 ;

END;

INTERNAL_INFO "bfenpin"
BEGIN
	DEVICE = EP1K30TC144-3;
    OD4P125 : LORAX = "1:FB4->LC1_A1|";
    OD1P124 : LORAX = "1:FB1|2:FH1R0,PA12R0C0->LC2_A1||";
    OD2P54  : LORAX = "1:FB2|2:FH2R0,PA6R0C0->LC3_A1||";
    OD3P56  : LORAX = "1:FB3|2:FH3R0,PA8R0C0->LC4_A1||";
    OD0P126 : LORAX = "1:FB0|2:FH0R0,PA7R0C0->LC5_A1||";
    OD5P55  : LORAX = "1:FB5->LC5_A1,->LC4_A1,->LC3_A1,->LC2_A1|2:CH1R0,PA10R0C0->LC1_A1,->LC5_A1,->LC4_A1,->LC3_A1,->LC2_A1||";
    LC1_A1  : LORAX = "1:MSW0R0C0,HHL23R0->OH8R0P102|";
	LC6_A1  : LORAX2 = "X, X, LC2_A1, LC3_A1";
	LC1_A1  : LORAX2 = "OD5P55, LC5_A1, LC4_A1, LC6_A1";
	LC5_A1  : LORAX2 = "OD0P126, LC5_A1, LC4_A1, LC6_A1";
	LC4_A1  : LORAX2 = "OD3P56, LC4_A1, LC7_A1, LC6_A1";
	LC3_A1  : LORAX2 = "OD2P54, LC7_A1, LC3_A1, LC2_A1";
	LC2_A1  : LORAX2 = "X, OD1P124, LC7_A1, LC2_A1";
	LC7_A1  : LORAX2 = "X, LC5_A1, LC4_A1, LC6_A1";
END;