phyuz.vhd

来自「这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity phyuz is
port(phaa,phab:in std_logic;
     clr_in2:out std_logic; 
     pha:out std_logic_vector(7 downto 0));
end phyuz;
architecture behav of phyuz is
signal acc:std_logic_vector(7 downto 0);
signal pha_clk:std_logic;
begin
pha_clk<=phaa or phab;
process(pha_clk)
begin
if(pha_clk'event and pha_clk='1')then
  if(acc>=180 )then acc<=(others=>'0');
    elsif(phaa='1')then acc<=acc+1;
       else acc<=acc+10;
         end if;
           end if;
end process;       
pha<=acc;
clr_in2<=pha_clk;
end behav;