sysclock.vhd

来自「这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sysclock is
port(clk:in std_logic;
     sysclk:out std_logic);
end sysclock;  
architecture behav of sysclock is
signal acc:std_logic_vector(2 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
   acc<=acc+1;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
   sysclk<=acc(2);
end if;
end process;
end behav;