achanle.rpt

这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）

  _EQ002 = !acc0 &  acc1 & !_LC2_E28
         #  acc0 & !acc1 & !_LC2_E28;

-- Node name is ':27' = 'acc2' 
-- Equation name is 'acc2', location is LC1_E28, type is buried.
acc2     = DFFE( _EQ003, GLOBAL( sysclk),  VCC,  VCC,  VCC);
  _EQ003 = !acc1 &  acc2 & !_LC2_E28
         # !acc0 &  acc2 & !_LC2_E28
         #  acc0 &  acc1 & !acc2 & !_LC2_E28;

-- Node name is ':26' = 'acc3' 
-- Equation name is 'acc3', location is LC7_E28, type is buried.
acc3     = DFFE( _EQ004, GLOBAL( sysclk),  VCC,  VCC,  VCC);
  _EQ004 =  acc3 & !_LC2_E28 & !_LC5_E28
         # !acc3 & !_LC2_E28 &  _LC5_E28;

-- Node name is ':25' = 'acc4' 
-- Equation name is 'acc4', location is LC2_E34, type is buried.
acc4     = DFFE( _EQ005, GLOBAL( sysclk),  VCC,  VCC,  VCC);
  _EQ005 =  acc4 & !_LC2_E28 & !_LC8_E28
         # !acc4 & !_LC2_E28 &  _LC8_E28;

-- Node name is ':24' = 'acc5' 
-- Equation name is 'acc5', location is LC4_E34, type is buried.
acc5     = DFFE( _EQ006, GLOBAL( sysclk),  VCC,  VCC,  VCC);
  _EQ006 = !acc4 &  acc5 & !_LC2_E28
         #  acc5 & !_LC2_E28 & !_LC8_E28
         #  acc4 & !acc5 & !_LC2_E28 &  _LC8_E28;

-- Node name is ':23' = 'acc6' 
-- Equation name is 'acc6', location is LC6_E34, type is buried.
acc6     = DFFE( _EQ007, GLOBAL( sysclk),  VCC,  VCC,  VCC);
  _EQ007 =  acc6 & !_LC2_E28 & !_LC7_E34
         # !acc5 &  acc6 & !_LC2_E28
         #  acc5 & !acc6 & !_LC2_E28 &  _LC7_E34;

-- Node name is ':22' = 'acc7' 
-- Equation name is 'acc7', location is LC3_E32, type is buried.
acc7     = DFFE( _EQ008, GLOBAL( sysclk),  VCC,  VCC,  VCC);
  _EQ008 =  acc7 & !_LC2_E28 & !_LC5_E34
         # !acc7 & !_LC2_E28 &  _LC5_E34;

-- Node name is ':21' = 'acc8' 
-- Equation name is 'acc8', location is LC4_E32, type is buried.
acc8     = DFFE( _EQ009, GLOBAL( sysclk),  VCC,  VCC,  VCC);
  _EQ009 = !acc7 &  acc8 & !_LC2_E28
         #  acc8 & !_LC2_E28 & !_LC5_E34
         #  acc7 & !acc8 & !_LC2_E28 &  _LC5_E34;

-- Node name is '|LPM_ADD_SUB:127|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_E28', type is buried 
!_LC5_E28 = _LC5_E28~NOT;
_LC5_E28~NOT = LCELL( _EQ010);
  _EQ010 = !acc2
         # !acc1
         # !acc0;

-- Node name is '|LPM_ADD_SUB:127|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_E28', type is buried 
_LC8_E28 = LCELL( _EQ011);
  _EQ011 =  acc0 &  acc1 &  acc2 &  acc3;

-- Node name is '|LPM_ADD_SUB:127|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_E34', type is buried 
_LC7_E34 = LCELL( _EQ012);
  _EQ012 =  acc4 &  _LC8_E28;

-- Node name is '|LPM_ADD_SUB:127|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_E34', type is buried 
_LC5_E34 = LCELL( _EQ013);
  _EQ013 =  acc4 &  acc5 &  acc6 &  _LC8_E28;

-- Node name is ':3' 
-- Equation name is '_LC2_E32', type is buried 
_LC2_E32 = DFFE( acc8, GLOBAL( sysclk),  VCC,  VCC,  VCC);

-- Node name is ':5' 
-- Equation name is '_LC1_E32', type is buried 
_LC1_E32 = DFFE( acc7, GLOBAL( sysclk),  VCC,  VCC,  VCC);

-- Node name is ':7' 
-- Equation name is '_LC8_E32', type is buried 
_LC8_E32 = DFFE( acc6, GLOBAL( sysclk),  VCC,  VCC,  VCC);

-- Node name is ':9' 
-- Equation name is '_LC3_E34', type is buried 
_LC3_E34 = DFFE( acc5, GLOBAL( sysclk),  VCC,  VCC,  VCC);

-- Node name is ':11' 
-- Equation name is '_LC1_E34', type is buried 
_LC1_E34 = DFFE( acc4, GLOBAL( sysclk),  VCC,  VCC,  VCC);

-- Node name is ':13' 
-- Equation name is '_LC8_E26', type is buried 
_LC8_E26 = DFFE( acc3, GLOBAL( sysclk),  VCC,  VCC,  VCC);

-- Node name is ':15' 
-- Equation name is '_LC5_E36', type is buried 
_LC5_E36 = DFFE( acc2, GLOBAL( sysclk),  VCC,  VCC,  VCC);

-- Node name is ':17' 
-- Equation name is '_LC7_E35', type is buried 
_LC7_E35 = DFFE( acc1, GLOBAL( sysclk),  VCC,  VCC,  VCC);

-- Node name is ':19' 
-- Equation name is '_LC6_E28', type is buried 
_LC6_E28 = DFFE( acc0, GLOBAL( sysclk),  VCC,  VCC,  VCC);

-- Node name is '~71~1' 
-- Equation name is '~71~1', location is LC8_E34, type is buried.
-- synthesized logic cell 
_LC8_E34 = LCELL( _EQ014);
  _EQ014 = !acc5
         #  acc4
         #  acc3;

-- Node name is '~71~2' 
-- Equation name is '~71~2', location is LC6_E32, type is buried.
-- synthesized logic cell 
_LC6_E32 = LCELL( _EQ015);
  _EQ015 = !acc6
         #  _LC8_E34
         # !acc8
         #  acc7;

-- Node name is ':81' 
-- Equation name is '_LC2_E28', type is buried 
!_LC2_E28 = _LC2_E28~NOT;
_LC2_E28~NOT = LCELL( _EQ016);
  _EQ016 = !clr_a & !_LC5_E28
         # !clr_a &  _LC6_E32;



Project Information               e:\mydesign\altera\maxplus\lisha\achanle.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:04


Memory Allocated
-----------------

Peak memory allocated during compilation  = 27,036K