📄 achanle.rpt
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** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - -- INPUT ^ 0 0 0 2 clr_a
55 - - - -- INPUT G ^ 0 0 0 0 sysclk
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\achanle.rpt
achanle
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
10 - - B -- OUTPUT 0 1 0 0 aadress0
29 - - E -- OUTPUT 0 1 0 0 aadress1
37 - - - 35 OUTPUT 0 1 0 0 aadress2
83 - - E -- OUTPUT 0 1 0 0 aadress3
87 - - E -- OUTPUT 0 1 0 0 aadress4
86 - - E -- OUTPUT 0 1 0 0 aadress5
28 - - E -- OUTPUT 0 1 0 0 aadress6
30 - - F -- OUTPUT 0 1 0 0 aadress7
27 - - E -- OUTPUT 0 1 0 0 aadress8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\achanle.rpt
achanle
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - E 28 OR2 ! 0 3 0 2 |LPM_ADD_SUB:127|addcore:adder|:79
- 8 - E 28 AND2 0 4 0 4 |LPM_ADD_SUB:127|addcore:adder|:83
- 7 - E 34 AND2 0 2 0 1 |LPM_ADD_SUB:127|addcore:adder|:87
- 5 - E 34 AND2 0 4 0 2 |LPM_ADD_SUB:127|addcore:adder|:95
- 2 - E 32 DFFE + 0 1 1 0 :3
- 1 - E 32 DFFE + 0 1 1 0 :5
- 8 - E 32 DFFE + 0 1 1 0 :7
- 3 - E 34 DFFE + 0 1 1 0 :9
- 1 - E 34 DFFE + 0 1 1 0 :11
- 8 - E 26 DFFE + 0 1 1 0 :13
- 5 - E 36 DFFE + 0 1 1 0 :15
- 7 - E 35 DFFE + 0 1 1 0 :17
- 6 - E 28 DFFE + 0 1 1 0 :19
- 4 - E 32 DFFE + 0 3 0 2 acc8 (:21)
- 3 - E 32 DFFE + 0 2 0 3 acc7 (:22)
- 6 - E 34 DFFE + 0 3 0 3 acc6 (:23)
- 4 - E 34 DFFE + 0 3 0 4 acc5 (:24)
- 2 - E 34 DFFE + 0 2 0 5 acc4 (:25)
- 7 - E 28 DFFE + 0 2 0 3 acc3 (:26)
- 1 - E 28 DFFE + 0 3 0 3 acc2 (:27)
- 4 - E 28 DFFE + 0 2 0 4 acc1 (:28)
- 3 - E 28 DFFE + 1 0 0 5 acc0 (:29)
- 8 - E 34 OR2 s 0 3 0 1 ~71~1
- 6 - E 32 OR2 s 0 4 0 1 ~71~2
- 2 - E 28 OR2 ! 1 2 0 8 :81
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\achanle.rpt
achanle
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 11/144( 7%) 0/ 72( 0%) 4/ 72( 5%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\achanle.rpt
achanle
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 sysclk
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\achanle.rpt
achanle
** EQUATIONS **
clr_a : INPUT;
sysclk : INPUT;
-- Node name is 'aadress0'
-- Equation name is 'aadress0', type is output
aadress0 = _LC6_E28;
-- Node name is 'aadress1'
-- Equation name is 'aadress1', type is output
aadress1 = _LC7_E35;
-- Node name is 'aadress2'
-- Equation name is 'aadress2', type is output
aadress2 = _LC5_E36;
-- Node name is 'aadress3'
-- Equation name is 'aadress3', type is output
aadress3 = _LC8_E26;
-- Node name is 'aadress4'
-- Equation name is 'aadress4', type is output
aadress4 = _LC1_E34;
-- Node name is 'aadress5'
-- Equation name is 'aadress5', type is output
aadress5 = _LC3_E34;
-- Node name is 'aadress6'
-- Equation name is 'aadress6', type is output
aadress6 = _LC8_E32;
-- Node name is 'aadress7'
-- Equation name is 'aadress7', type is output
aadress7 = _LC1_E32;
-- Node name is 'aadress8'
-- Equation name is 'aadress8', type is output
aadress8 = _LC2_E32;
-- Node name is ':29' = 'acc0'
-- Equation name is 'acc0', location is LC3_E28, type is buried.
acc0 = DFFE( _EQ001, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ001 = !acc0 & !clr_a;
-- Node name is ':28' = 'acc1'
-- Equation name is 'acc1', location is LC4_E28, type is buried.
acc1 = DFFE( _EQ002, GLOBAL( sysclk), VCC, VCC, VCC);
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