bchanle.vhd

来自「这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bchanle is
port(bchclk,clr_b:in std_logic;
     badress:out std_logic_vector(8 downto 0));
end bchanle;
architecture behav of bchanle is
signal acc:std_logic_vector(8 downto 0);
begin
process(bchclk)
begin
if(bchclk'event and bchclk='1')then
   if(clr_b='1'or acc>=359)then acc<=(others=>'0');
     else acc<=acc+1;
       end if;
          end if;
              end process;
process(bchclk)
begin
if(bchclk'event and bchclk='1')then
   badress<=acc;
   end if;
   end process;
   end behav;