bchanle.rpt

这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）

         # !acc5 &  acc6 & !_LC1_A3
         #  acc5 & !acc6 & !_LC1_A3 &  _LC8_A2;

-- Node name is ':22' = 'acc7' 
-- Equation name is 'acc7', location is LC4_A3, type is buried.
acc7     = DFFE( _EQ008, GLOBAL( bchclk),  VCC,  VCC,  VCC);
  _EQ008 =  acc7 & !_LC1_A3 & !_LC7_A2
         # !acc7 & !_LC1_A3 &  _LC7_A2;

-- Node name is ':21' = 'acc8' 
-- Equation name is 'acc8', location is LC5_A3, type is buried.
acc8     = DFFE( _EQ009, GLOBAL( bchclk),  VCC,  VCC,  VCC);
  _EQ009 = !acc7 &  acc8 & !_LC1_A3
         #  acc8 & !_LC1_A3 & !_LC7_A2
         #  acc7 & !acc8 & !_LC1_A3 &  _LC7_A2;

-- Node name is 'badress0' 
-- Equation name is 'badress0', type is output 
badress0 =  _LC4_A1;

-- Node name is 'badress1' 
-- Equation name is 'badress1', type is output 
badress1 =  _LC3_A1;

-- Node name is 'badress2' 
-- Equation name is 'badress2', type is output 
badress2 =  _LC7_A1;

-- Node name is 'badress3' 
-- Equation name is 'badress3', type is output 
badress3 =  _LC5_A4;

-- Node name is 'badress4' 
-- Equation name is 'badress4', type is output 
badress4 =  _LC8_A5;

-- Node name is 'badress5' 
-- Equation name is 'badress5', type is output 
badress5 =  _LC5_A2;

-- Node name is 'badress6' 
-- Equation name is 'badress6', type is output 
badress6 =  _LC3_A2;

-- Node name is 'badress7' 
-- Equation name is 'badress7', type is output 
badress7 =  _LC2_A3;

-- Node name is 'badress8' 
-- Equation name is 'badress8', type is output 
badress8 =  _LC3_A3;

-- Node name is '|LPM_ADD_SUB:160|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A1', type is buried 
_LC2_A1  = LCELL( _EQ010);
  _EQ010 =  acc0 &  acc1 &  acc2 &  acc3;

-- Node name is '|LPM_ADD_SUB:160|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A2', type is buried 
_LC8_A2  = LCELL( _EQ011);
  _EQ011 =  acc4 &  _LC2_A1;

-- Node name is '|LPM_ADD_SUB:160|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A2', type is buried 
_LC7_A2  = LCELL( _EQ012);
  _EQ012 =  acc4 &  acc5 &  acc6 &  _LC2_A1;

-- Node name is ':3' 
-- Equation name is '_LC3_A3', type is buried 
_LC3_A3  = DFFE( acc8, GLOBAL( bchclk),  VCC,  VCC,  VCC);

-- Node name is ':5' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = DFFE( acc7, GLOBAL( bchclk),  VCC,  VCC,  VCC);

-- Node name is ':7' 
-- Equation name is '_LC3_A2', type is buried 
_LC3_A2  = DFFE( acc6, GLOBAL( bchclk),  VCC,  VCC,  VCC);

-- Node name is ':9' 
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = DFFE( acc5, GLOBAL( bchclk),  VCC,  VCC,  VCC);

-- Node name is ':11' 
-- Equation name is '_LC8_A5', type is buried 
_LC8_A5  = DFFE( acc4, GLOBAL( bchclk),  VCC,  VCC,  VCC);

-- Node name is ':13' 
-- Equation name is '_LC5_A4', type is buried 
_LC5_A4  = DFFE( acc3, GLOBAL( bchclk),  VCC,  VCC,  VCC);

-- Node name is ':15' 
-- Equation name is '_LC7_A1', type is buried 
_LC7_A1  = DFFE( acc2, GLOBAL( bchclk),  VCC,  VCC,  VCC);

-- Node name is ':17' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = DFFE( acc1, GLOBAL( bchclk),  VCC,  VCC,  VCC);

-- Node name is ':19' 
-- Equation name is '_LC4_A1', type is buried 
_LC4_A1  = DFFE( acc0, GLOBAL( bchclk),  VCC,  VCC,  VCC);

-- Node name is ':81' 
-- Equation name is '_LC1_A2', type is buried 
_LC1_A2  = LCELL( _EQ013);
  _EQ013 =  _LC2_A2
         # !acc6
         # !acc5;

-- Node name is ':88' 
-- Equation name is '_LC2_A2', type is buried 
_LC2_A2  = LCELL( _EQ014);
  _EQ014 = !acc3 & !acc4 &  _LC1_A1;

-- Node name is ':101' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ015);
  _EQ015 = !acc2
         # !acc1
         # !acc0;

-- Node name is ':114' 
-- Equation name is '_LC1_A3', type is buried 
!_LC1_A3 = _LC1_A3~NOT;
_LC1_A3~NOT = LCELL( _EQ016);
  _EQ016 = !acc8 & !clr_b
         # !acc7 & !clr_b &  _LC1_A2;



Project Information                                       f:\lisha\bchanle.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = off
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 24,639K