📄 test.rpt
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_LC7_E12 = LCELL( _EQ012);
_EQ012 = _LC2_E7 & _LC2_E18 & _LC4_E7;
-- Node name is '|ACHANLE:3|LPM_ADD_SUB:127|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_E12', type is buried
_LC8_E12 = LCELL( _EQ013);
_EQ013 = _LC3_E7 & _LC4_E12 & _LC7_E12;
-- Node name is '|ACHANLE:3|:3'
-- Equation name is '_LC1_E2', type is buried
_LC1_E2 = DFFE( _LC3_E12, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is '|ACHANLE:3|:5'
-- Equation name is '_LC7_E4', type is buried
_LC7_E4 = DFFE( _LC1_E12, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is '|ACHANLE:3|:7'
-- Equation name is '_LC1_E11', type is buried
_LC1_E11 = DFFE( _LC4_E12, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is '|ACHANLE:3|:9'
-- Equation name is '_LC5_E7', type is buried
_LC5_E7 = DFFE( _LC3_E7, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is '|ACHANLE:3|:11'
-- Equation name is '_LC8_E7', type is buried
_LC8_E7 = DFFE( _LC2_E7, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is '|ACHANLE:3|:13'
-- Equation name is '_LC1_E7', type is buried
_LC1_E7 = DFFE( _LC4_E7, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is '|ACHANLE:3|:15'
-- Equation name is '_LC4_E18', type is buried
_LC4_E18 = DFFE( _LC5_E18, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is '|ACHANLE:3|:17'
-- Equation name is '_LC3_E18', type is buried
_LC3_E18 = DFFE( _LC6_E18, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is '|ACHANLE:3|:19'
-- Equation name is '_LC1_E18', type is buried
_LC1_E18 = DFFE( _LC7_E18, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is '|ACHANLE:3|~71~1'
-- Equation name is '_LC5_E12', type is buried
-- synthesized logic cell
_LC5_E12 = LCELL( _EQ014);
_EQ014 = !_LC4_E12
# _LC1_E12
# !_LC3_E12;
-- Node name is '|ACHANLE:3|~71~2'
-- Equation name is '_LC6_E12', type is buried
-- synthesized logic cell
_LC6_E12 = LCELL( _EQ015);
_EQ015 = !_LC3_E7
# _LC5_E12
# _LC4_E7
# _LC2_E7;
-- Node name is '|ACHANLE:3|:81'
-- Equation name is '_LC2_E12', type is buried
!_LC2_E12 = _LC2_E12~NOT;
_LC2_E12~NOT = LCELL( _EQ016);
_EQ016 = !_LC2_E18 & !_LC8_E18
# _LC6_E12 & !_LC8_E18;
-- Node name is '|HZ100:6|:14' = '|HZ100:6|acc0'
-- Equation name is '_LC3_E13', type is buried
_LC3_E13 = DFFE(!_LC3_E13, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is '|HZ100:6|:13' = '|HZ100:6|acc1'
-- Equation name is '_LC1_E13', type is buried
_LC1_E13 = DFFE( _EQ017, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ017 = !_LC1_E13 & _LC3_E13
# _LC1_E13 & !_LC3_E13;
-- Node name is '|HZ100:6|:12' = '|HZ100:6|acc2'
-- Equation name is '_LC4_E13', type is buried
_LC4_E13 = DFFE( _EQ018, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ018 = !_LC3_E13 & _LC4_E13
# !_LC1_E13 & _LC4_E13
# _LC1_E13 & _LC3_E13 & !_LC4_E13;
-- Node name is '|HZ100:6|:11' = '|HZ100:6|acc3'
-- Equation name is '_LC6_E13', type is buried
_LC6_E13 = DFFE( _EQ019, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ019 = !_LC5_E13 & _LC6_E13
# _LC5_E13 & !_LC6_E13;
-- Node name is '|HZ100:6|:10' = '|HZ100:6|acc4'
-- Equation name is '_LC7_E13', type is buried
_LC7_E13 = DFFE( _EQ020, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ020 = !_LC6_E13 & _LC7_E13
# !_LC5_E13 & _LC7_E13
# _LC5_E13 & _LC6_E13 & !_LC7_E13;
-- Node name is '|HZ100:6|:9' = '|HZ100:6|acc5'
-- Equation name is '_LC1_E8', type is buried
_LC1_E8 = DFFE( _EQ021, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ021 = _LC1_E8 & !_LC2_E13
# !_LC1_E8 & _LC2_E13;
-- Node name is '|HZ100:6|:8' = '|HZ100:6|acc6'
-- Equation name is '_LC2_E8', type is buried
_LC2_E8 = DFFE( _EQ022, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ022 = !_LC1_E8 & _LC2_E8
# _LC2_E8 & !_LC2_E13
# _LC1_E8 & !_LC2_E8 & _LC2_E13;
-- Node name is '|HZ100:6|:7' = '|HZ100:6|acc7'
-- Equation name is '_LC3_E8', type is buried
_LC3_E8 = DFFE( _EQ023, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ023 = !_LC1_E8 & _LC3_E8
# !_LC2_E13 & _LC3_E8
# !_LC2_E8 & _LC3_E8
# _LC1_E8 & _LC2_E8 & _LC2_E13 & !_LC3_E8;
-- Node name is '|HZ100:6|:6' = '|HZ100:6|acc8'
-- Equation name is '_LC6_E8', type is buried
_LC6_E8 = DFFE( _EQ024, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ024 = !_LC4_E8 & _LC6_E8
# _LC4_E8 & !_LC6_E8;
-- Node name is '|HZ100:6|:5' = '|HZ100:6|acc9'
-- Equation name is '_LC7_E8', type is buried
_LC7_E8 = DFFE( _EQ025, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ025 = !_LC6_E8 & _LC7_E8
# !_LC4_E8 & _LC7_E8
# _LC4_E8 & _LC6_E8 & !_LC7_E8;
-- Node name is '|HZ100:6|:4' = '|HZ100:6|acc10'
-- Equation name is '_LC8_E8', type is buried
_LC8_E8 = DFFE( _EQ026, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ026 = !_LC6_E8 & _LC8_E8
# !_LC4_E8 & _LC8_E8
# !_LC7_E8 & _LC8_E8
# _LC4_E8 & _LC6_E8 & _LC7_E8 & !_LC8_E8;
-- Node name is '|HZ100:6|LPM_ADD_SUB:48|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_E13', type is buried
_LC5_E13 = LCELL( _EQ027);
_EQ027 = _LC1_E13 & _LC3_E13 & _LC4_E13;
-- Node name is '|HZ100:6|LPM_ADD_SUB:48|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_E13', type is buried
_LC2_E13 = LCELL( _EQ028);
_EQ028 = _LC5_E13 & _LC6_E13 & _LC7_E13;
-- Node name is '|HZ100:6|LPM_ADD_SUB:48|addcore:adder|:107' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_E8', type is buried
_LC4_E8 = LCELL( _EQ029);
_EQ029 = _LC1_E8 & _LC2_E8 & _LC2_E13 & _LC3_E8;
-- Node name is '|HZ100:6|:2'
-- Equation name is '_LC5_E8', type is buried
_LC5_E8 = DFFE( _LC8_E8, GLOBAL( sysclk), VCC, VCC, VCC);
-- Node name is ':7'
-- Equation name is '_LC8_E18', type is buried
_LC8_E18 = DFFE( clr, _LC5_E8, VCC, VCC, VCC);
-- Node name is '|arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC3_E', type is memory
_EC3_E = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC9_E', type is memory
_EC9_E = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_E', type is memory
_EC2_E = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC11_E', type is memory
_EC11_E = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_E', type is memory
_EC4_E = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC10_E', type is memory
_EC10_E = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_E', type is memory
_EC1_E = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC12_E', type is memory
_EC12_E = MEMORY_SEGMENT( VCC, GLOBAL( sysclk), VCC, GND, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, _LC1_E18, _LC3_E18, _LC4_E18, _LC1_E7, _LC8_E7, _LC5_E7, _LC1_E11, _LC7_E4, _LC1_E2, VCC, VCC, VCC, VCC, VCC);
Project Information e:\mydesign\altera\maxplus\lisha\test.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,421K
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