📄 test.rpt
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that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\test.rpt
test
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
86 - - E -- OUTPUT 0 1 0 0 adata0
29 - - E -- OUTPUT 0 1 0 0 adata1
27 - - E -- OUTPUT 0 1 0 0 adata2
83 - - E -- OUTPUT 0 1 0 0 adata3
9 - - B -- OUTPUT 0 1 0 0 adata4
12 - - C -- OUTPUT 0 1 0 0 adata5
13 - - C -- OUTPUT 0 1 0 0 adata6
20 - - D -- OUTPUT 0 1 0 0 adata7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\test.rpt
test
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - E 18 OR2 ! 0 3 0 5 |ACHANLE:3|LPM_ADD_SUB:127|addcore:adder|:79
- 6 - E 07 AND2 0 2 0 1 |ACHANLE:3|LPM_ADD_SUB:127|addcore:adder|:83
- 7 - E 12 AND2 0 3 0 2 |ACHANLE:3|LPM_ADD_SUB:127|addcore:adder|:87
- 8 - E 12 AND2 0 3 0 2 |ACHANLE:3|LPM_ADD_SUB:127|addcore:adder|:95
- 1 - E 02 DFFE + 0 1 0 8 |ACHANLE:3|:3
- 7 - E 04 DFFE + 0 1 0 8 |ACHANLE:3|:5
- 1 - E 11 DFFE + 0 1 0 8 |ACHANLE:3|:7
- 5 - E 07 DFFE + 0 1 0 8 |ACHANLE:3|:9
- 8 - E 07 DFFE + 0 1 0 8 |ACHANLE:3|:11
- 1 - E 07 DFFE + 0 1 0 8 |ACHANLE:3|:13
- 4 - E 18 DFFE + 0 1 0 8 |ACHANLE:3|:15
- 3 - E 18 DFFE + 0 1 0 8 |ACHANLE:3|:17
- 1 - E 18 DFFE + 0 1 0 8 |ACHANLE:3|:19
- 3 - E 12 DFFE + 0 3 0 2 |ACHANLE:3|acc8 (|ACHANLE:3|:21)
- 1 - E 12 DFFE + 0 2 0 3 |ACHANLE:3|acc7 (|ACHANLE:3|:22)
- 4 - E 12 DFFE + 0 3 0 3 |ACHANLE:3|acc6 (|ACHANLE:3|:23)
- 3 - E 07 DFFE + 0 3 0 4 |ACHANLE:3|acc5 (|ACHANLE:3|:24)
- 2 - E 07 DFFE + 0 3 0 4 |ACHANLE:3|acc4 (|ACHANLE:3|:25)
- 4 - E 07 DFFE + 0 2 0 5 |ACHANLE:3|acc3 (|ACHANLE:3|:26)
- 5 - E 18 DFFE + 0 3 0 2 |ACHANLE:3|acc2 (|ACHANLE:3|:27)
- 6 - E 18 DFFE + 0 2 0 3 |ACHANLE:3|acc1 (|ACHANLE:3|:28)
- 7 - E 18 DFFE + 0 1 0 4 |ACHANLE:3|acc0 (|ACHANLE:3|:29)
- 5 - E 12 OR2 s 0 3 0 1 |ACHANLE:3|~71~1
- 6 - E 12 OR2 s 0 4 0 1 |ACHANLE:3|~71~2
- 2 - E 12 OR2 ! 0 3 0 8 |ACHANLE:3|:81
- - 3 E -- MEM_SGMT 0 9 1 0 |arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 9 E -- MEM_SGMT 0 9 1 0 |arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 2 E -- MEM_SGMT 0 9 1 0 |arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 11 E -- MEM_SGMT 0 9 1 0 |arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 4 E -- MEM_SGMT 0 9 1 0 |arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 10 E -- MEM_SGMT 0 9 1 0 |arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 1 E -- MEM_SGMT 0 9 1 0 |arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 12 E -- MEM_SGMT 0 9 1 0 |arom:2|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- 5 - E 13 AND2 0 3 0 3 |HZ100:6|LPM_ADD_SUB:48|addcore:adder|:87
- 2 - E 13 AND2 0 3 0 4 |HZ100:6|LPM_ADD_SUB:48|addcore:adder|:95
- 4 - E 08 AND2 0 4 0 3 |HZ100:6|LPM_ADD_SUB:48|addcore:adder|:107
- 5 - E 08 DFFE + 0 1 0 1 |HZ100:6|:2
- 8 - E 08 DFFE + 0 3 0 1 |HZ100:6|acc10 (|HZ100:6|:4)
- 7 - E 08 DFFE + 0 2 0 1 |HZ100:6|acc9 (|HZ100:6|:5)
- 6 - E 08 DFFE + 0 1 0 2 |HZ100:6|acc8 (|HZ100:6|:6)
- 3 - E 08 DFFE + 0 3 0 1 |HZ100:6|acc7 (|HZ100:6|:7)
- 2 - E 08 DFFE + 0 2 0 2 |HZ100:6|acc6 (|HZ100:6|:8)
- 1 - E 08 DFFE + 0 1 0 3 |HZ100:6|acc5 (|HZ100:6|:9)
- 7 - E 13 DFFE + 0 2 0 1 |HZ100:6|acc4 (|HZ100:6|:10)
- 6 - E 13 DFFE + 0 1 0 2 |HZ100:6|acc3 (|HZ100:6|:11)
- 4 - E 13 DFFE + 0 2 0 1 |HZ100:6|acc2 (|HZ100:6|:12)
- 1 - E 13 DFFE + 0 1 0 2 |HZ100:6|acc1 (|HZ100:6|:13)
- 3 - E 13 DFFE + 0 0 0 3 |HZ100:6|acc0 (|HZ100:6|:14)
- 8 - E 18 DFFE 1 1 0 2 :7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\test.rpt
test
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 2/144( 1%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
D: 1/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
E: 25/144( 17%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\test.rpt
test
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 38 sysclk
DFF 1 |HZ100:6|:2
Device-Specific Information: e:\mydesign\altera\maxplus\lisha\test.rpt
test
** EQUATIONS **
clr : INPUT;
sysclk : INPUT;
-- Node name is 'adata0'
-- Equation name is 'adata0', type is output
adata0 = _EC3_E;
-- Node name is 'adata1'
-- Equation name is 'adata1', type is output
adata1 = _EC9_E;
-- Node name is 'adata2'
-- Equation name is 'adata2', type is output
adata2 = _EC2_E;
-- Node name is 'adata3'
-- Equation name is 'adata3', type is output
adata3 = _EC11_E;
-- Node name is 'adata4'
-- Equation name is 'adata4', type is output
adata4 = _EC4_E;
-- Node name is 'adata5'
-- Equation name is 'adata5', type is output
adata5 = _EC10_E;
-- Node name is 'adata6'
-- Equation name is 'adata6', type is output
adata6 = _EC1_E;
-- Node name is 'adata7'
-- Equation name is 'adata7', type is output
adata7 = _EC12_E;
-- Node name is '|ACHANLE:3|:29' = '|ACHANLE:3|acc0'
-- Equation name is '_LC7_E18', type is buried
_LC7_E18 = DFFE( _EQ001, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ001 = !_LC7_E18 & !_LC8_E18;
-- Node name is '|ACHANLE:3|:28' = '|ACHANLE:3|acc1'
-- Equation name is '_LC6_E18', type is buried
_LC6_E18 = DFFE( _EQ002, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ002 = !_LC2_E12 & !_LC6_E18 & _LC7_E18
# !_LC2_E12 & _LC6_E18 & !_LC7_E18;
-- Node name is '|ACHANLE:3|:27' = '|ACHANLE:3|acc2'
-- Equation name is '_LC5_E18', type is buried
_LC5_E18 = DFFE( _EQ003, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ003 = !_LC2_E12 & _LC5_E18 & !_LC7_E18
# !_LC2_E12 & _LC5_E18 & !_LC6_E18
# !_LC2_E12 & !_LC5_E18 & _LC6_E18 & _LC7_E18;
-- Node name is '|ACHANLE:3|:26' = '|ACHANLE:3|acc3'
-- Equation name is '_LC4_E7', type is buried
_LC4_E7 = DFFE( _EQ004, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ004 = !_LC2_E12 & !_LC2_E18 & _LC4_E7
# !_LC2_E12 & _LC2_E18 & !_LC4_E7;
-- Node name is '|ACHANLE:3|:25' = '|ACHANLE:3|acc4'
-- Equation name is '_LC2_E7', type is buried
_LC2_E7 = DFFE( _EQ005, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ005 = _LC2_E7 & !_LC2_E12 & !_LC4_E7
# _LC2_E7 & !_LC2_E12 & !_LC2_E18
# !_LC2_E7 & !_LC2_E12 & _LC2_E18 & _LC4_E7;
-- Node name is '|ACHANLE:3|:24' = '|ACHANLE:3|acc5'
-- Equation name is '_LC3_E7', type is buried
_LC3_E7 = DFFE( _EQ006, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ006 = !_LC2_E7 & !_LC2_E12 & _LC3_E7
# !_LC2_E12 & _LC3_E7 & !_LC6_E7
# _LC2_E7 & !_LC2_E12 & !_LC3_E7 & _LC6_E7;
-- Node name is '|ACHANLE:3|:23' = '|ACHANLE:3|acc6'
-- Equation name is '_LC4_E12', type is buried
_LC4_E12 = DFFE( _EQ007, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ007 = !_LC2_E12 & !_LC3_E7 & _LC4_E12
# !_LC2_E12 & _LC4_E12 & !_LC7_E12
# !_LC2_E12 & _LC3_E7 & !_LC4_E12 & _LC7_E12;
-- Node name is '|ACHANLE:3|:22' = '|ACHANLE:3|acc7'
-- Equation name is '_LC1_E12', type is buried
_LC1_E12 = DFFE( _EQ008, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ008 = _LC1_E12 & !_LC2_E12 & !_LC8_E12
# !_LC1_E12 & !_LC2_E12 & _LC8_E12;
-- Node name is '|ACHANLE:3|:21' = '|ACHANLE:3|acc8'
-- Equation name is '_LC3_E12', type is buried
_LC3_E12 = DFFE( _EQ009, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ009 = !_LC1_E12 & !_LC2_E12 & _LC3_E12
# !_LC2_E12 & _LC3_E12 & !_LC8_E12
# _LC1_E12 & !_LC2_E12 & !_LC3_E12 & _LC8_E12;
-- Node name is '|ACHANLE:3|LPM_ADD_SUB:127|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_E18', type is buried
!_LC2_E18 = _LC2_E18~NOT;
_LC2_E18~NOT = LCELL( _EQ010);
_EQ010 = !_LC5_E18
# !_LC7_E18
# !_LC6_E18;
-- Node name is '|ACHANLE:3|LPM_ADD_SUB:127|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_E7', type is buried
_LC6_E7 = LCELL( _EQ011);
_EQ011 = _LC2_E18 & _LC4_E7;
-- Node name is '|ACHANLE:3|LPM_ADD_SUB:127|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_E12', type is buried
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