hz100.vhd

来自「这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hz100 is
port(sysclk:in std_logic;
     clk_hu:out std_logic);
end hz100;  
architecture behav of hz100 is
signal acc:std_logic_vector(8 downto 0);
begin
process(sysclk)
begin
if(sysclk'event and sysclk='1')then
   acc<=acc+1;
end if;
end process;
process(sysclk)
begin
if(sysclk'event and sysclk='1')then
   clk_hu<=acc(8);
end if;
end process;
end behav;