phader.rpt
来自「这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器」· RPT 代码 · 共 734 行 · 第 1/3 页
RPT
734 行
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\lisha\phader.rpt
phader
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
96 - - C -- OUTPUT 0 1 0 0 badress0
91 - - D -- OUTPUT 0 1 0 0 badress1
72 - - - 03 OUTPUT 0 1 0 0 badress2
112 - - - 04 OUTPUT 0 1 0 0 badress3
99 - - B -- OUTPUT 0 1 0 0 badress4
81 - - F -- OUTPUT 0 1 0 0 badress5
97 - - C -- OUTPUT 0 1 0 0 badress6
92 - - D -- OUTPUT 0 1 0 0 badress7
86 - - E -- OUTPUT 0 1 0 0 badress8
90 - - D -- OUTPUT 0 1 0 0 badress9
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\lisha\phader.rpt
phader
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 03 OR2 4 0 0 2 |LPM_ADD_SUB:123|addcore:adder|pcarry1
- 7 - A 03 OR2 2 1 0 2 |LPM_ADD_SUB:123|addcore:adder|pcarry2
- 3 - A 03 OR2 2 1 0 2 |LPM_ADD_SUB:123|addcore:adder|pcarry3
- 8 - A 01 OR2 2 1 0 2 |LPM_ADD_SUB:123|addcore:adder|pcarry4
- 4 - A 01 OR2 2 1 0 2 |LPM_ADD_SUB:123|addcore:adder|pcarry5
- 7 - A 02 OR2 2 1 0 3 |LPM_ADD_SUB:123|addcore:adder|pcarry6
- 5 - A 02 DFFE + 0 1 1 0 :19
- 4 - A 02 DFFE + 0 1 1 0 :21
- 1 - A 02 DFFE + 0 1 1 0 :23
- 1 - A 01 DFFE + 0 1 1 0 :25
- 2 - A 01 DFFE + 0 1 1 0 :27
- 3 - A 01 DFFE + 0 1 1 0 :29
- 1 - A 03 DFFE + 0 1 1 0 :31
- 2 - A 03 DFFE + 0 1 1 0 :33
- 3 - A 04 DFFE + 0 1 1 0 :35
- 4 - A 04 DFFE + 0 1 1 0 :37
- 2 - A 02 DFFE + 3 1 0 1 acc9 (:39)
- 3 - A 02 DFFE + 3 1 0 1 acc8 (:40)
- 6 - A 02 DFFE + 2 1 0 1 acc7 (:41)
- 7 - A 01 DFFE + 2 1 0 1 acc6 (:42)
- 6 - A 01 DFFE + 2 1 0 1 acc5 (:43)
- 5 - A 01 DFFE + 2 1 0 1 acc4 (:44)
- 5 - A 03 DFFE + 2 1 0 1 acc3 (:45)
- 4 - A 03 DFFE + 2 1 0 1 acc2 (:46)
- 1 - A 04 DFFE + 4 0 0 1 acc1 (:47)
- 2 - A 04 DFFE + 2 0 0 1 acc0 (:48)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\lisha\phader.rpt
phader
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/144( 3%) 9/ 72( 12%) 0/ 72( 0%) 5/16( 31%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
D: 0/144( 0%) 3/ 72( 4%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
E: 0/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 0/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 4/24( 16%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\lisha\phader.rpt
phader
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 sysclk
Device-Specific Information: f:\lisha\phader.rpt
phader
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
b4 : INPUT;
b5 : INPUT;
b6 : INPUT;
b7 : INPUT;
b8 : INPUT;
sysclk : INPUT;
-- Node name is ':48' = 'acc0'
-- Equation name is 'acc0', location is LC2_A4, type is buried.
acc0 = DFFE( _EQ001, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ001 = a0 & !b0
# !a0 & b0;
-- Node name is ':47' = 'acc1'
-- Equation name is 'acc1', location is LC1_A4, type is buried.
acc1 = DFFE( _EQ002, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ002 = a0 & a1 & b0 & b1
# !a0 & !a1 & b1
# !a1 & !b0 & b1
# !a0 & a1 & !b1
# a1 & !b0 & !b1
# a0 & !a1 & b0 & !b1;
-- Node name is ':46' = 'acc2'
-- Equation name is 'acc2', location is LC4_A3, type is buried.
acc2 = DFFE( _EQ003, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ003 = a2 & b2 & _LC6_A3
# !a2 & b2 & !_LC6_A3
# a2 & !b2 & !_LC6_A3
# !a2 & !b2 & _LC6_A3;
-- Node name is ':45' = 'acc3'
-- Equation name is 'acc3', location is LC5_A3, type is buried.
acc3 = DFFE( _EQ004, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ004 = a3 & b3 & _LC7_A3
# !a3 & b3 & !_LC7_A3
# a3 & !b3 & !_LC7_A3
# !a3 & !b3 & _LC7_A3;
-- Node name is ':44' = 'acc4'
-- Equation name is 'acc4', location is LC5_A1, type is buried.
acc4 = DFFE( _EQ005, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ005 = a4 & b4 & _LC3_A3
# !a4 & b4 & !_LC3_A3
# a4 & !b4 & !_LC3_A3
# !a4 & !b4 & _LC3_A3;
-- Node name is ':43' = 'acc5'
-- Equation name is 'acc5', location is LC6_A1, type is buried.
acc5 = DFFE( _EQ006, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ006 = a5 & b5 & _LC8_A1
# !a5 & !b5 & _LC8_A1
# !a5 & b5 & !_LC8_A1
# a5 & !b5 & !_LC8_A1;
-- Node name is ':42' = 'acc6'
-- Equation name is 'acc6', location is LC7_A1, type is buried.
acc6 = DFFE( _EQ007, GLOBAL( sysclk), VCC, VCC, VCC);
_EQ007 = a6 & b6 & _LC4_A1
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