spi_master.rpt

spi总线的vhdl代码

	spi_intrface_spi_ctrl_sm_BIT_CNTR/q_int_Madd__add0000__and0000);


spi_intrface_spi_ctrl_sm__not0003 <= ((NOT uc_intrface_rcv_full_reset)
	OR (rcv_load));


spi_intrface_spi_ctrl_sm__xor0004 <= ((spi_intrface_spi_ctrl_sm__xor00046)
	OR (spi_intrface_spi_ctrl_sm__xor00045));


spi_intrface_spi_ctrl_sm__xor00041 <= (sck AND uc_intrface_cpol);


spi_intrface_spi_ctrl_sm__xor00045 <= (NOT spi_intrface_SCK_GEN_sck_d1 AND 
	spi_intrface_spi_ctrl_sm__xor00041);


spi_intrface_spi_ctrl_sm__xor00046 <= (NOT sck AND spi_intrface_SCK_GEN_sck_d1 AND 
	NOT uc_intrface_cpol);


spi_intrface_spi_ctrl_sm__xor0008 <= ((NOT uc_intrface_spien)
	OR (NOT uc_intrface_xmit_empty_reset));

FDCPE_spi_intrface_spi_ctrl_sm_bit_cnt0: FDCPE port map (spi_intrface_spi_ctrl_sm_bit_cnt(0),NOT spi_intrface_spi_ctrl_sm_bit_cnt(0),spi_intrface_sck_1,NOT spi_intrface_spi_ctrl_sm_bit_cnt_reset,'0',spi_intrface_spi_ctrl_sm_bit_cnt_rst);

FDCPE_spi_intrface_spi_ctrl_sm_bit_cnt1: FDCPE port map (spi_intrface_spi_ctrl_sm_bit_cnt(1),spi_intrface_spi_ctrl_sm_bit_cnt_D(1),spi_intrface_sck_1,NOT spi_intrface_spi_ctrl_sm_bit_cnt_reset,'0',spi_intrface_spi_ctrl_sm_bit_cnt_rst);
spi_intrface_spi_ctrl_sm_bit_cnt_D(1) <= spi_intrface_spi_ctrl_sm_bit_cnt(0)
	XOR spi_intrface_spi_ctrl_sm_bit_cnt(1);

FDCPE_spi_intrface_spi_ctrl_sm_bit_cnt2: FDCPE port map (spi_intrface_spi_ctrl_sm_bit_cnt(2),spi_intrface_spi_ctrl_sm_bit_cnt_D(2),spi_intrface_sck_1,NOT spi_intrface_spi_ctrl_sm_bit_cnt_reset,'0',spi_intrface_spi_ctrl_sm_bit_cnt_rst);
spi_intrface_spi_ctrl_sm_bit_cnt_D(2) <= spi_intrface_spi_ctrl_sm_BIT_CNTR/q_int_Madd__add0000__and0000
	XOR spi_intrface_spi_ctrl_sm_bit_cnt(2);

FDCPE_spi_intrface_spi_ctrl_sm_bit_cnt3: FDCPE port map (spi_intrface_spi_ctrl_sm_bit_cnt(3),spi_intrface_spi_ctrl_sm_bit_cnt_D(3),spi_intrface_sck_1,NOT spi_intrface_spi_ctrl_sm_bit_cnt_reset,'0',spi_intrface_spi_ctrl_sm_bit_cnt_rst);
spi_intrface_spi_ctrl_sm_bit_cnt_D(3) <= spi_intrface_spi_ctrl_sm_BIT_CNTR/q_int_Madd__add0000__and0001
	XOR spi_intrface_spi_ctrl_sm_bit_cnt(3);


spi_intrface_spi_ctrl_sm_bit_cnt_reset <= (spi_intrface_spi_ctrl_sm_ss_in_int AND 
	spi_intrface_spi_ctrl_sm_bit_cnt_rst);


spi_intrface_spi_ctrl_sm_bit_cnt_rst <= ((spi_intrface_spi_ctrl_sm_spi_state_Out43)
	OR (spi_intrface_spi_ctrl_sm_spi_state_Out44));


spi_intrface_spi_ctrl_sm_clk0_mask <= (uc_intrface_cpha AND uc_intrface_start);


spi_intrface_spi_ctrl_sm_clk0_mask10 <= ((NOT spi_intrface_spi_ctrl_sm_spi_state_FFd3)
	OR (spi_intrface_spi_ctrl_sm_clk0_mask9));


spi_intrface_spi_ctrl_sm_clk0_mask6 <= (spi_intrface_spi_ctrl_sm_clk0_mask AND NOT xmit_empty);


spi_intrface_spi_ctrl_sm_clk0_mask7 <= (NOT uc_intrface_cpha AND 
	NOT spi_intrface_spi_ctrl_sm__xor0004);


spi_intrface_spi_ctrl_sm_clk0_mask8 <= ((spi_intrface_spi_ctrl_sm_clk0_mask6)
	OR (spi_intrface_spi_ctrl_sm_clk0_mask7));


spi_intrface_spi_ctrl_sm_clk0_mask9 <= (NOT spi_intrface_spi_ctrl_sm_spi_state_FFd4 AND 
	spi_intrface_spi_ctrl_sm_clk0_mask8);

FTCPE_spi_intrface_spi_ctrl_sm_spi_state_FFd1: FTCPE port map (spi_intrface_spi_ctrl_sm_spi_state_FFd1,spi_intrface_spi_ctrl_sm_spi_state_FFd1_T,clk,spi_intrface_xmit_shift_reg__xor0001,'0','1');
spi_intrface_spi_ctrl_sm_spi_state_FFd1_T <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd1/Q/D AND 
	NOT spi_intrface_spi_ctrl_sm_spi_state_FFd1)
	OR (NOT spi_intrface_spi_ctrl_sm_spi_state_FFd1/Q/D AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd1));


spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T <= (spi_intrface_spi_ctrl_sm_spi_state_FFd3 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T9);


spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T1 <= (spi_intrface_SCK_GEN_sck_int_d1 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd1);


spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T4 <= (spi_intrface_spi_ctrl_sm_spi_state_FFd2 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd4);


spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T6 <= (NOT spi_intrface_SCK_GEN_sck_int AND 
	NOT spi_intrface_spi_ctrl_sm_spi_state_FFd4);


spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T7 <= (NOT spi_intrface_spi_ctrl_sm_spi_state_FFd1 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T4);


spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T8 <= (spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T1 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T6);


spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T9 <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T8)
	OR (spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T7));


spi_intrface_spi_ctrl_sm_spi_state_FFd1/Q/D <= spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T
	XOR spi_intrface_spi_ctrl_sm_spi_state_FFd1;

FTCPE_spi_intrface_spi_ctrl_sm_spi_state_FFd2: FTCPE port map (spi_intrface_spi_ctrl_sm_spi_state_FFd2,spi_intrface_spi_ctrl_sm_spi_state_FFd2_T,clk,spi_intrface_xmit_shift_reg__xor0001,'0','1');
spi_intrface_spi_ctrl_sm_spi_state_FFd2_T <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd2/Q/D AND 
	NOT spi_intrface_spi_ctrl_sm_spi_state_FFd2)
	OR (NOT spi_intrface_spi_ctrl_sm_spi_state_FFd2/Q/D AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd2));


spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T <= (spi_intrface_spi_ctrl_sm_spi_state_FFd3 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T9);


spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T1 <= (uc_intrface_cpha AND uc_intrface_start);


spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T3 <= (spi_intrface_SCK_GEN_sck_int AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd4);


spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T5 <= (spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T1 AND 
	NOT xmit_empty);


spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T6 <= (NOT spi_intrface_SCK_GEN_sck_int_d1 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T3);


spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T7 <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd4)
	OR (spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T5));


spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T8 <= (spi_intrface_spi_ctrl_sm_spi_state_FFd2 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T7);


spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T9 <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T8)
	OR (spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T6));


spi_intrface_spi_ctrl_sm_spi_state_FFd2/Q/D <= spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T
	XOR spi_intrface_spi_ctrl_sm_spi_state_FFd2;

FTCPE_spi_intrface_spi_ctrl_sm_spi_state_FFd3: FTCPE port map (spi_intrface_spi_ctrl_sm_spi_state_FFd3,spi_intrface_spi_ctrl_sm_spi_state_FFd3_T,clk,spi_intrface_xmit_shift_reg__xor0001,'0','1');
spi_intrface_spi_ctrl_sm_spi_state_FFd3_T <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd3/Q/D AND 
	NOT spi_intrface_spi_ctrl_sm_spi_state_FFd3)
	OR (NOT spi_intrface_spi_ctrl_sm_spi_state_FFd3/Q/D AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd3));


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T18)
	OR (spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T16));


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T1 <= (spi_intrface_spi_ctrl_sm_spi_state_FFd2 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd3);


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T11 <= (spi_intrface_SCK_GEN_sck_int AND 
	NOT spi_intrface_SCK_GEN_sck_int_d1 AND NOT spi_intrface_spi_ctrl_sm_spi_state_FFd2);


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T12 <= (NOT spi_intrface_spi_ctrl_sm_spi_state_FFd2 AND 
	NOT spi_intrface_spi_ctrl_sm_spi_state_FFd4);


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T13 <= (NOT spi_intrface_spi_ctrl_sm_spi_state_FFd3 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd4 AND spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T8);


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T14 <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T11)
	OR (spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T1));


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T15 <= (spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T5 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T12);


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T16 <= (NOT spi_intrface_spi_ctrl_sm_spi_state_FFd1 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd4 AND spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T14);


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T17 <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T13)
	OR (spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T15));


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T18 <= (NOT spi_intrface_SCK_GEN_sck_int AND 
	spi_intrface_SCK_GEN_sck_int_d1 AND spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T17);


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T5 <= (spi_intrface_spi_ctrl_sm_spi_state_FFd1 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd3);


spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T8 <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd1)
	OR (spi_intrface_spi_ctrl_sm_spi_state_FFd2));


spi_intrface_spi_ctrl_sm_spi_state_FFd3/Q/D <= spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T
	XOR spi_intrface_spi_ctrl_sm_spi_state_FFd3;

FTCPE_spi_intrface_spi_ctrl_sm_spi_state_FFd4: FTCPE port map (spi_intrface_spi_ctrl_sm_spi_state_FFd4,spi_intrface_spi_ctrl_sm_spi_state_FFd4_T,clk,spi_intrface_xmit_shift_reg__xor0001,'0','1');
spi_intrface_spi_ctrl_sm_spi_state_FFd4_T <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd4/Q/D AND 
	NOT spi_intrface_spi_ctrl_sm_spi_state_FFd4)
	OR (NOT spi_intrface_spi_ctrl_sm_spi_state_FFd4/Q/D AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd4));


spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T <= ((spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T40)
	OR (spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T45)
	OR (spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T41));


spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T14 <= (spi_intrface_spi_ctrl_sm_spi_state_FFd2 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd4);


spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T2 <= (sck AND uc_intrface_cpol);


spi_i