spi_master.rpt

spi总线的vhdl代码

spi_intrface_SCK_GEN_Mmux__mux0005_Result13 <= (uc_intrface_cpol AND 
	spi_intrface_SCK_GEN_Mmux__mux0005_Result11);


spi_intrface_SCK_GEN_Mmux__mux0005_Result15 <= (NOT uc_intrface_cpol AND 
	NOT spi_intrface_SCK_GEN_Mmux__mux0005_Result12);


spi_intrface_SCK_GEN_Mmux__mux0005_Result7 <= (uc_intrface_cpha AND NOT spi_intrface_sck_1);


spi_intrface_SCK_GEN_Mmux__mux0005_Result8 <= (NOT spi_intrface_SCK_GEN_sck_0 AND NOT uc_intrface_cpha);


spi_intrface_SCK_GEN_Mmux__mux0005_Result9 <= (uc_intrface_cpha AND NOT spi_intrface_sck_1);


spi_intrface_SCK_GEN_Mmux__mux0006_Result <= (spi_intrface_SCK_GEN_clk_cnt(4) AND 
	uc_intrface_clkdiv(1));


spi_intrface_SCK_GEN_Mmux__mux0006_Result10 <= (NOT uc_intrface_clkdiv(0) AND 
	spi_intrface_SCK_GEN_Mmux__mux0006_Result8);


spi_intrface_SCK_GEN_Mmux__mux0006_Result2 <= (spi_intrface_SCK_GEN_clk_cnt(3) AND 
	uc_intrface_clkdiv(1));


spi_intrface_SCK_GEN_Mmux__mux0006_Result5 <= (spi_intrface_SCK_GEN_clk_cnt(2) AND 
	NOT uc_intrface_clkdiv(1));


spi_intrface_SCK_GEN_Mmux__mux0006_Result6 <= (spi_intrface_SCK_GEN_clk_cnt(1) AND 
	NOT uc_intrface_clkdiv(1));


spi_intrface_SCK_GEN_Mmux__mux0006_Result7 <= ((spi_intrface_SCK_GEN_Mmux__mux0006_Result5)
	OR (spi_intrface_SCK_GEN_Mmux__mux0006_Result));


spi_intrface_SCK_GEN_Mmux__mux0006_Result8 <= ((spi_intrface_SCK_GEN_Mmux__mux0006_Result6)
	OR (spi_intrface_SCK_GEN_Mmux__mux0006_Result2));


spi_intrface_SCK_GEN_Mmux__mux0006_Result9 <= (uc_intrface_clkdiv(0) AND 
	spi_intrface_SCK_GEN_Mmux__mux0006_Result7);


spi_intrface_SCK_GEN__mux000410 <= (NOT spi_intrface_SCK_GEN_clk_cnt(3) AND 
	uc_intrface_clkdiv(1));


spi_intrface_SCK_GEN__mux000411 <= (NOT spi_intrface_SCK_GEN_clk_cnt(1) AND 
	NOT uc_intrface_clkdiv(1));


spi_intrface_SCK_GEN__mux000412 <= ((spi_intrface_SCK_GEN__mux00048)
	OR (spi_intrface_SCK_GEN__mux00049));


spi_intrface_SCK_GEN__mux000413 <= ((spi_intrface_SCK_GEN__mux000410)
	OR (spi_intrface_SCK_GEN__mux000411));


spi_intrface_SCK_GEN__mux000414 <= (uc_intrface_clkdiv(0) AND 
	spi_intrface_SCK_GEN__mux000412);


spi_intrface_SCK_GEN__mux000415 <= (NOT uc_intrface_clkdiv(0) AND 
	spi_intrface_SCK_GEN__mux000413);


spi_intrface_SCK_GEN__mux000416 <= ((spi_intrface_SCK_GEN__mux000414)
	OR (spi_intrface_SCK_GEN__mux000415));


spi_intrface_SCK_GEN__mux00048 <= (NOT spi_intrface_SCK_GEN_clk_cnt(4) AND 
	uc_intrface_clkdiv(1));


spi_intrface_SCK_GEN__mux00049 <= (NOT spi_intrface_SCK_GEN_clk_cnt(2) AND 
	NOT uc_intrface_clkdiv(1));

FDCPE_spi_intrface_SCK_GEN_clk_cnt1: FDCPE port map (spi_intrface_SCK_GEN_clk_cnt(1),spi_intrface_SCK_GEN_clk_cnt_D(1),clk,spi_intrface_xmit_shift_reg__xor0001,'0','1');
spi_intrface_SCK_GEN_clk_cnt_D(1) <= spi_intrface_SCK_GEN_CLK_DIVDR/qout(0)
	XOR spi_intrface_SCK_GEN_clk_cnt(1);

FDCPE_spi_intrface_SCK_GEN_clk_cnt2: FDCPE port map (spi_intrface_SCK_GEN_clk_cnt(2),spi_intrface_SCK_GEN_clk_cnt_D(2),clk,spi_intrface_xmit_shift_reg__xor0001,'0','1');
spi_intrface_SCK_GEN_clk_cnt_D(2) <= spi_intrface_SCK_GEN_CLK_DIVDR/q_int_Madd__add0000__and0000
	XOR spi_intrface_SCK_GEN_clk_cnt(2);

FDCPE_spi_intrface_SCK_GEN_clk_cnt3: FDCPE port map (spi_intrface_SCK_GEN_clk_cnt(3),spi_intrface_SCK_GEN_clk_cnt_D(3),clk,spi_intrface_xmit_shift_reg__xor0001,'0','1');
spi_intrface_SCK_GEN_clk_cnt_D(3) <= spi_intrface_SCK_GEN_CLK_DIVDR/q_int_Madd__add0000__and0001
	XOR spi_intrface_SCK_GEN_clk_cnt(3);

FDCPE_spi_intrface_SCK_GEN_clk_cnt4: FDCPE port map (spi_intrface_SCK_GEN_clk_cnt(4),spi_intrface_SCK_GEN_clk_cnt_D(4),clk,spi_intrface_xmit_shift_reg__xor0001,'0','1');
spi_intrface_SCK_GEN_clk_cnt_D(4) <= spi_intrface_SCK_GEN_CLK_DIVDR/q_int_Madd__add0000__and0002
	XOR spi_intrface_SCK_GEN_clk_cnt(4);

FDCPE_spi_intrface_SCK_GEN_sck_0: FDCPE port map (spi_intrface_SCK_GEN_sck_0,spi_intrface_SCK_GEN_sck_0_D,clk,NOT uc_intrface_spien,'0','1');
spi_intrface_SCK_GEN_sck_0_D <= (spi_intrface_clk0_mask AND 
	spi_intrface_SCK_GEN__mux000416);


spi_intrface_SCK_GEN_sck_110 <= ((spi_intrface_SCK_GEN_sck_19)
	OR (spi_intrface_SCK_GEN_sck_16));


spi_intrface_SCK_GEN_sck_13 <= (spi_intrface_spi_ctrl_sm_spi_state_FFd3 AND 
	spi_intrface_spi_ctrl_sm_spi_state_FFd4);


spi_intrface_SCK_GEN_sck_15 <= ((uc_intrface_cpha)
	OR (NOT spi_intrface_spi_ctrl_sm__xor0004));


spi_intrface_SCK_GEN_sck_16 <= (NOT spi_intrface_spi_ctrl_sm_spi_state_FFd2 AND 
	spi_intrface_SCK_GEN_sck_13);


spi_intrface_SCK_GEN_sck_17 <= (NOT spi_intrface_spi_ctrl_sm_spi_state_FFd4 AND 
	spi_intrface_SCK_GEN_sck_15);


spi_intrface_SCK_GEN_sck_18 <= ((NOT spi_intrface_spi_ctrl_sm_spi_state_FFd3)
	OR (spi_intrface_SCK_GEN_sck_17));


spi_intrface_SCK_GEN_sck_19 <= (spi_intrface_spi_ctrl_sm_spi_state_FFd2 AND 
	spi_intrface_SCK_GEN_sck_18);

FDCPE_spi_intrface_SCK_GEN_sck_d1: FDCPE port map (spi_intrface_SCK_GEN_sck_d1,sck,clk,NOT uc_intrface_spien,'0','1');

FDCPE_spi_intrface_SCK_GEN_sck_int: FDCPE port map (spi_intrface_SCK_GEN_sck_int,spi_intrface_SCK_GEN_sck_int_D,clk,NOT uc_intrface_spien,'0','1');
spi_intrface_SCK_GEN_sck_int_D <= ((spi_intrface_SCK_GEN_Mmux__mux0006_Result9)
	OR (spi_intrface_SCK_GEN_Mmux__mux0006_Result10));

FDCPE_spi_intrface_SCK_GEN_sck_int_d1: FDCPE port map (spi_intrface_SCK_GEN_sck_int_d1,spi_intrface_SCK_GEN_sck_int,clk,NOT uc_intrface_spien,'0','1');


spi_intrface_clk0_mask <= (spi_intrface_spi_ctrl_sm_spi_state_FFd2 AND 
	spi_intrface_spi_ctrl_sm_clk0_mask10);


spi_intrface_rcv_shift_reg/_and0000 <= (uc_intrface_rcv_cpol AND spi_intrface_sck_re);


spi_intrface_rcv_shift_reg/_and000010 <= (NOT spi_intrface_rcv_shift_reg/rcv_bitcnt_int(1) AND 
	NOT spi_intrface_rcv_shift_reg/rcv_bitcnt_int(2));


spi_intrface_rcv_shift_reg/_and000011 <= (spi_intrface_rcv_shift_reg/rcv_bitcnt_int(2) AND 
	NOT uc_intrface_rcv_cpol);


spi_intrface_rcv_shift_reg/_and000012 <= ((spi_intrface_rcv_shift_reg/_and0000)
	OR (spi_intrface_rcv_shift_reg/_and00009));


spi_intrface_rcv_shift_reg/_and000013 <= (spi_intrface_rcv_shift_reg/_and00006 AND 
	spi_intrface_rcv_shift_reg/_and000011);


spi_intrface_rcv_shift_reg/_and000014 <= (NOT spi_intrface_rcv_shift_reg/rcv_bitcnt_int(0) AND 
	spi_intrface_rcv_shift_reg/_and000012 AND spi_intrface_rcv_shift_reg/_and000010);


spi_intrface_rcv_shift_reg/_and000015 <= ((spi_intrface_rcv_shift_reg/_and000014)
	OR (spi_intrface_rcv_shift_reg/_and000013));


spi_intrface_rcv_shift_reg/_and00006 <= (spi_intrface_rcv_shift_reg/rcv_bitcnt_int(0) AND 
	spi_intrface_rcv_shift_reg/rcv_bitcnt_int(1) AND uc_intrface_cpol AND spi_intrface_sck_fe);


spi_intrface_rcv_shift_reg/_and00009 <= (NOT uc_intrface_cpol AND NOT uc_intrface_rcv_cpol AND 
	spi_intrface_sck_fe);


spi_intrface_rcv_shift_reg/_or0000 <= ((NOT uc_intrface_spien)
	OR (ss_n_int));


spi_intrface_rcv_shift_reg/_xor0000 <= ((NOT spi_intrface_spi_ctrl_sm_ss_in_int)
	OR (NOT uc_intrface_spien));

FDCPE_spi_intrface_rcv_shift_reg/miso_neg: FDCPE port map (spi_intrface_rcv_shift_reg/miso_neg,miso,NOT sck.PIN,spi_intrface_rcv_shift_reg/_xor0000,'0','1');

FDCPE_spi_intrface_rcv_shift_reg/miso_pos: FDCPE port map (spi_intrface_rcv_shift_reg/miso_pos,miso,sck.PIN,spi_intrface_rcv_shift_reg/_xor0000,'0','1');

FDCPE_spi_intrface_rcv_shift_reg/rcv_bitcnt_int0: FDCPE port map (spi_intrface_rcv_shift_reg/rcv_bitcnt_int(0),NOT spi_intrface_rcv_shift_reg/rcv_bitcnt_int(0),sck.PIN,spi_intrface_rcv_shift_reg/_or0000,'0','1');

FDCPE_spi_intrface_rcv_shift_reg/rcv_bitcnt_int1: FDCPE port map (spi_intrface_rcv_shift_reg/rcv_bitcnt_int(1),spi_intrface_rcv_shift_reg/rcv_bitcnt_int_D(1),sck.PIN,spi_intrface_rcv_shift_reg/_or0000,'0','1');
spi_intrface_rcv_shift_reg/rcv_bitcnt_int_D(1) <= spi_intrface_rcv_shift_reg/rcv_bitcnt_int(0)
	XOR spi_intrface_rcv_shift_reg/rcv_bitcnt_int(1);

FDCPE_spi_intrface_rcv_shift_reg/rcv_bitcnt_int2: FDCPE port map (spi_intrface_rcv_shift_reg/rcv_bitcnt_int(2),spi_intrface_rcv_shift_reg/rcv_bitcnt_int_D(2),sck.PIN,spi_intrface_rcv_shift_reg/_or0000,'0','1');
spi_intrface_rcv_shift_reg/rcv_bitcnt_int_D(2) <= spi_intrface_rcv_shift_reg/rcv_bitcnt_int_Madd__add0000__and0000
	XOR spi_intrface_rcv_shift_reg/rcv_bitcnt_int(2);


spi_intrface_rcv_shift_reg/rcv_bitcnt_int_Madd__add0000__and0000 <= (spi_intrface_rcv_shift_reg/rcv_bitcnt_int(0) AND 
	spi_intrface_rcv_shift_reg/rcv_bitcnt_int(1));


spi_intrface_rcv_shift_reg/shift_in1 <= (spi_intrface_rcv_shift_reg/miso_pos AND 
	uc_intrface_rcv_cpol);


spi_intrface_rcv_shift_reg/shift_in3 <= (spi_intrface_rcv_shift_reg/miso_neg AND 
	NOT uc_intrface_rcv_cpol);


spi_intrface_sck_1 <= (spi_intrface_SCK_GEN_sck_int AND 
	spi_intrface_SCK_GEN_sck_110);


spi_intrface_sck_fe <= (NOT sck AND spi_intrface_SCK_GEN_sck_d1);


spi_intrface_sck_re <= (sck AND NOT spi_intrface_SCK_GEN_sck_d1);


spi_intrface_spi_ctrl_sm_BIT_CNTR/q_int_Madd__add0000__and0000 <= (spi_intrface_spi_ctrl_sm_bit_cnt(0) AND 
	spi_intrface_spi_ctrl_sm_bit_cnt(1));


spi_intrface_spi_ctrl_sm_BIT_CNTR/q_int_Madd__add0000__and0001 <= (spi_intrface_spi_ctrl_sm_bit_cnt(2) AND